Resynchronizing the M24xxx’s internal logic

AN1471

2/4

Doc ID 8335 Rev 4

1.2

The interrupted transmission was an outgoing data byte

(during a READ instruction)

A tricky configuration might be reached if, after loosing the bus communication control, the

M24xxx memory is stopped when outputting a 0 on SDA. In such a case, even if the bus

Master transmits a Start condition, the M24xxx memory cannot decode it as the SDA bus

line is forced to 0. A good way to work around this state is to have the bus Master sending

several clock cycles until the M24xxx outputs a 1: once the 1 state has been output, the bus

Master sends a Start condition which will be correctly decoded by the M24xxx memory.

This result is always reached using a blind [9 Start + Stop] sequence, with two possible

outcomes:

1.

worst case: when it lost the bus communication control, the M24xxx memory device

was starting to clock out eight 0s (the data byte was 00h), as shown in Figure 1.

As the ninth clock pulse makes the M24xxx output a NoAck state (“SDAout from

memory device” is 1), the falling edge of “SDAout from bus Master” correctly drives the

SDA bus line and this event is decoded as a Start condition by the M24xxx memory.

2.

standard case: when it lost the bus communication control, the M24xxx memory

device was starting to clock out a byte composed of 0s and 1s; the Start condition is

decoded sooner, that is with the first bit of data “SDAout from memory device” =1. In

such a case, the M24xxx memory decodes N successive Start conditions (one Start

condition for each “SDAout from memory device” =1) which restart the M24xxx memory

N times, before decoding the final Stop condition (see Figure 1).

Caution:

Resynchronization does not modify the internal address counter.

In order to define the internal address counter value, the next instruction must be either a

Byte Random Read, a Sequential Random Read or a Write (because the current Read or

Sequential Read instruction does not modify the internal address counter).

Figure 1.

Nine attempts at a Start condition and then a Stop condition

1.

The Stop condition following the Start condition sets the M24xxx in Standby mode.

1.3

Conclusion

The blind [9 Start + Stop] sequence shown in Figure 1 is specially designed to ensure that

the I²C bus Master will, at the end of this sequence, succeed the resynchronization of the

M24xxx.

AI02406c

SDAout from

bus Master

SCL from

bus Master

3

456

12

7

8

9

SDAout from

memory

device

SDA bus

0000

00

00

NoACK