LTC2912 datasheet(7/14 Pages) LINER

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LTC2912

2912fb

For more information www.linear.com/LTC2912

BLOCK DIAGRAM

0.5V

–

UVLO

VCC

–

VCC

OV PULSE

GENERATOR

DISABLE

OV LATCH

CLEAR/BYPASS

LTC2912-1, LTC2912-3

TMR

VCC

OV/OV

LATCH 8

2µA

DIS

GND

2912 BD

UV PULSE

GENERATOR

OSCILLATOR

VCC

400k

LTC2912-1

LTC2912-2

LTC2912-3

LTC2912-2

OV (Pin 6/Pin 3, LTC2912-3): Overvoltage Logic Output.

Asserts high with a weak internal pull‑up to VCC when the

VL input is above threshold. Latches high. May be pulled

above VCC using an external pull‑up. Leave pin open if

unused.

TMR (Pin 4/Pin 5): Reset Delay Timer. Attach an external

capacitor (CTMR) of at least 10pF to GND to set a reset

delay time of 9ms/nF. A 1nF capacitor will generate an

8.5ms reset delay time. Tie pin to VCC to bypass timer.

UV (Pin 7/Pin 2): Undervoltage Logic Output. Asserts low

when the VH input voltage is below threshold. Held low

for a programmed delay time after the VH input is valid.

Pin has a weak pull‑up to VCC and may be pulled above

VCC using an external pull‑up. Leave pin open if unused.

VCC (Pin 1/Pin 8): Supply Voltage. Bypass this pin to

GND with a 0.1µF (or greater) capacitor. Operates as a

direct supply input for voltages up to 6V. Operates as a

shunt regulator for supply voltages greater than 6V and

should have a resistance between the pin and the supply

to limit input current to no greater than 10mA. When used

without a current‑limiting resistance, pin voltage must

not exceed 6V.

VH (Pin 2/Pin 7): Voltage High Input. When the voltage

on this pin is below 0.5V, an undervoltage condition is

triggered. Tie pin to VCC if unused.

VL (Pin 3/Pin 6): Voltage Low Input. When the voltage

on this pin is above 0.5V, an overvoltage condition is

triggered. Tie pin to GND if unused.

PIN FUNCTIONS (DFN/TSOT Packages)

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