LTC2913

9

2913fb

UV/OV Timing

holds OV or UV asserted after all faults have cleared. This

assures a minimum reset pulse width allowing a settling

time delay for the monitored voltage after it has entered

the valid region of operation.

When any VH input drops below its designed threshold,

the UV pin asserts low. When all inputs recover above

their designed thresholds, the UV output timer starts. If

all inputs remain above their designed thresholds when

the timer finishes, the UV pin weakly pulls high. However,

if any input falls below its designed threshold during this

timeout period, the timer resets and restarts when all inputs

are above the designed thresholds. The OV output behaves

as the UV output when LATCH is high (LTC2913-1).

Selecting the UV/OV Timing Capacitor

is adjustable to accommodate a variety of applications.

ground sets the timeout period. The value of capacitor

needed for a particular timeout period is:

The Reset Timeout Period vs Capacitance graph found in

the Typical Performance Characteristics shows the desired

delay time as a function of the value of the timer capacitor

that must be used. The TMR pin must have a minimum

only limitation is the availability of a large value capacitor

with low leakage. Capacitor leakage current must not exceed

the minimum TMR charging current of 1.3μA. Tying the

Undervoltage Lockout

undervoltage lockout (UVLO) condition. During UVLO,

UV is asserted and pulled low while OV is cleared and

follows the same timing procedure as an undervoltage

condition on any input.

Shunt Regulator

operates as a direct supply input for voltages up to 6V.

Under this condition, the quiescent current of the device

than 6V, the device operates as a shunt regulator and must

to limit the current to no greater than 10mA.

When choosing this resistance value, select an appropriate

location on the I-V curve shown in the Typical Performance

UV and OV Output Characteristics

The DC characteristics of the UV and 0V pull-down strength

are shown in the Typical Performance Characteristics. Each

down to ground. This arrangement allows these pins to

have open-drain behavior while possessing several other

beneficial characteristics. The weak pull-up eliminates the

need for an external pull-up resistor when the rise time on

the pin is not critical. On the other hand, the open-drain

configuration allows for wired-OR connections, and is

useful when more than one signal needs to pull down

0.15V at UV.

on. Therefore, an external pull-up resistor of no more than

100k is recommended on the OV pin if the state and pull-up

Note however, by adding an external pull-up resistor, the

pull-up strength on the OV pin is increased. Therefore, if

it is connected in a wired-OR connection, the pull-down

strength of any single device must accommodate this

additional pull-up strength.

Output Rise and Fall Time Estimation

The UV and OV outputs have strong pull-down capabil-

ity. The following formula estimates the output fall time

(90% to 10%) for a particular external load capacitance

APPLICATIONS INFORMATION