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BACK EMF DETECTION DURING PWM ON TIME BY ST7MC

t0~t1: The capacitor starts to discharge by the inductance. At the beginning, since the capac-

itance is small, the discharging rate is very fast, but as the voltage reduces, the rate drops. At

time t1, the capacitor is fully discharged, and the diode D turns on. The current passes through

the diode and the voltage is kept around -0.7v.

t1~t1': The current will decrease linearly from peak to zero because the inductor is reset by

(Vd+3/2ec). Vd is the voltage drop of the diode. Large inductance will keep the clamp time

longer. At time t1', the inductor current is reset to zero. The back EMF signal shows up in the

winding terminal.

Since the back EMF is detected at the end of PWM off period, which is at t2, it is important that

the clamp should be ended before t2; otherwise the controller won't be able to detect the zero

crossing. Because of the settling time of the resonant transient during PWM off time, the max-

imum PWM duty is far from 100% duty cycle.

If the back EMF can be detected during on time at high duty cycle, then there is enough time

for the resonant transient to settle down. The next chapter explains how to implement it.