LTC4412HV datasheet(6/12 Pages) LINER

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LTC4412HV

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OPERATIO

Operation can best be understood by referring to the Block

Diagram, which illustrates the internal circuit blocks along

with the few external components, and the graph that

accompanies Figure 1. The terms primary and auxiliary are

arbitrary and may be changed to suit the application.

Operation begins when either or both power sources are

applied and the CTL control pin is below the input low

voltage of 0.35V (VIL). If only the primary supply is

present, the Power Source Selector will power the

LTC4412HV from the VIN pin. Amplifier A1 will deliver a

current to the Analog Controller block that is proportional

to the voltage difference in the VIN and SENSE pins. While

the voltage on SENSE is lower than VIN – 20mV (VFR), the

Analog Controller will instruct the Linear Gate Driver and

Voltage Clamp block to pull down the GATE pin voltage and

turn on the external P-channel MOSFET. The dynamic pull-

down current of 50

µA (IG(SNK)) stops when the GATE

voltage reaches ground or the gate clamp voltage. The

gate clamp voltage is 7V (VG(ON)) below the higher of VIN

or VSENSE. As the SENSE voltage pulls up to VIN – 20mV,

the LTC4412HV will regulate the GATE voltage to maintain

a 20mV difference between VIN and VSENSE which is also

the VDS of the MOSFET. The system is now in the forward

regulation mode and the load will be powered from the

primary supply. As the load current varies, the GATE

voltage will be controlled to maintain the 20mV difference.

If the load current exceeds the P-channel MOSFET’s ability

to deliver the current with a 20mV VDS the GATE voltage

will clamp, the MOSFET will behave as a fixed resistor and

the forward voltage will increase slightly. While the MOSFET

is on the STAT pin is an open circuit.

When an auxiliary supply is applied, the SENSE pin will be

pulled higher than the VIN pin through the external diode.

The Power Source Selector will power the LTC4412HV

from the SENSE pin. As the SENSE voltage pulls above

VIN – 20mV, the Analog Controller will instruct the Linear

Gate Driver and Voltage Clamp block to pull the GATE

voltage up to turn off the P-channel MOSFET. When the

voltage on SENSE is higher than VIN + 20mV (VRTO), the

Analog Controller will instruct the Linear Gate Driver and

Voltage Clamp block to rapidly pull the GATE pin voltage

to the SENSE pin voltage. This action will quickly finish

turning off the external P-channel MOSFET if it hasn’t

already turned completely off. For a clean transistion, the

reverse turn-off threshold has hysteresis to prevent

uncertainty. The system is now in the reverse turn-off

mode. Power to the load is being delivered through the

external diode and no current is drawn from the primary

supply. The external diode provides protection in case

the auxiliary supply is below the primary supply, sinks

current to ground or is connected reverse polarity. Dur-

ing the reverse turn-off mode of operation the STAT pin

will sink 10

µA of current (IS(SNK)) if connected. Note that

the external MOSFET is wired so that the drain to source

diode will momentarily forward bias when power is first

applied to VIN and will become reverse biased when an

auxiliary supply is applied.

When the CTL (control) input is asserted high, the external

MOSFET will have its gate to source voltage forced to a

small voltage VG(OFF) and the STAT pin will sink 10µA of

current if connected. This feature is useful to allow control

input switching of the load between two power sources as

shown in Figure 4 or as a switchable high side driver as

shown in Figure 7. A 3.5

µA internal pull- down current

(ICTL) on the CTL pin will insure a low level input if the pin

should become open.

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