AN2452 datasheet(5/21 Pages) STMICROELECTRONICS

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AN2452

Software

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Output divider:

–

Direct output.

–

Divider by 2.

–

Divider by 4.

Configurations:

–

Load/Save: load/save a configuration file.

–

Load default/Save default: load/save a default configuration.

10. Program counter B: 12-bit counter.

11. VCO. VCO settings:

–

Output frequency range/VCOs frequency range: press this button to show

information on the limits of Fout/Fvco (only for the embedded VCOs).

–

VCO selection (enabled only in Advanced mode):

- EXT: external VCO. The external VCO buffer is able to manage a signal coming

from an external VCO in order to build a synthesizer using the STW8110x only as

PLL IC. The external VCO signal can range from 625 MHz up to 5 GHz. Its

minimum power level must be -10 dBm.

- VCO A/VCO B: embedded VCOs.

12. Parallel port address. Hex value of the parallel port base address:

–

278: normally assigned to LPT2.

–

378: normally assigned to LPT1.

–3BC

–

FILE: output is saved to a text file.

13. Prescaler modulus:

–P=16

–P=19

14. Reference divider. The 10-bit programmable reference counter allows the input

reference frequency to be divided to produce the input clock to the phase frequency

detector (PFD):

Fpfd = Fref / R

where

–Fpfd: PFD input frequency

–Fref: input reference frequency

Limits: 2

≤R ≤1023

15. Frequency settings:

–Fref: input reference frequency (MHz)

- Limits: 10 MHz

≤Fref ≤200 MHz

–Fpfd: phase frequency detector (PFD) input frequency (kHz)

Fpfd = Fref / R, where R is the reference divider factor.

–

-/+: finds a lower/higher rational value for Fpfd.

–Fvco: VCO oscillating frequency (MHz)

Fvco = N · Fpfd.

–

N: PLL division ratio

N = B

· P + A.

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