AN2551

Configuring STR91xFA for best performance

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memory map). When the CPU makes a buffered write operation through the DTCM to the

SRAM, there will be zero delay, even if SRAM arbitration is currently granted to the AHB at

the time of the DTCM write operation. A similar benefit can be enjoyed when the CPU writes

to the peripheral on the AHB/APB, decoupling the CPU from waits associated with a busy

bus or peripheral. However, care must be taken using buffered writes to preserve data

coherency. For example, if the AHB has just written a value to SRAM while a buffered write

is pending from the DTCM for the very same SRAM address, then when arbitration is

granted to back the DTCM, the most current value just written by the AHB will be overwritten

by the DTCM. If this situation would cause a problem in your system, then non buffered

writes are required.

2.4

Pre-Fetch Queue (PFQ), Branch Cache (BC) accelerator

The PFQ/BC memory accelerator can be enabled and disabled by firmware. By default, the

PFQ/BC is enabled, but it's important to ensure that your initialization firmware has not

disabled the PFQ/BC unintentionally (bit0 of register SCU_SCR0).

Early versions of STR91x firmware library from ST contained a mistake in the initialization

code which disabled the PFQ/BC.

Additionally, in the first version of production silicon, STR91xF (RevD), the depth of the PFQ

is set to four instructions by default, and firmware must write to bit 0 of the FMI control

register FMI_CR to specify a PFQ depth of 8 instructions to achieve optimum CPU

performance. However, in the current production silicon STR91xFA (RevG), the depth of the

PFQ is fixed at eight instructions and it cannot be changed, ensuring optimum performance.

2.5

Instruction-set mode

32-bit architectures have a higher performance when manipulating 32-bit data. For

applications needing best performance, STR91xFA should be used in ARM (32-bit) mode.