AN2586

Power supplies

Doc ID 13675 Rev 7

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1.3.2

Programmable voltage detector (PVD)

selected by the PLS[2:0] bits in the Power control register (PWR_CR).

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate

EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD

configuration. As an example the service routine can perform emergency shutdown tasks.

Figure 4.

PVD thresholds

1.3.3

System reset

A system reset sets all registers to their reset values except for the reset flags in the clock

controller CSR register and the registers in the Backup domain (see Figure 1).

A system reset is generated when one of the following events occurs:

1.

A low level on the NRST pin (external reset)

2.

window watchdog end-of-count condition (WWDG reset)

3.

Independent watchdog end-of-count condition (IWDG reset)

4.

A software reset (SW reset)

5.

Low-power management reset

The reset source can be identified by checking the reset flags in the Control/Status register,

RCC_CSR.

100 mV

hysteresis

PVD threshold

PVD output

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