AN2593

STR91x vectored interrupt controller VIC

5/15

1.2.2

FIQ interrupt management

For FIQ there are no priority levels. When an enabled FIQ interrupt occurs, the VIC signals it

directly to the ARM core by asserting the FIQ interrupt line.

Then the ARM core switches to FIQ mode, and goes to address 0x1C where you must

implement the FIQ interrupt handler.

Normally in order to lower FIQ interrupt latency only one interrupt should be configured as

FIQ. But it is possible to configure several interrupts as FIQ, and in this case the application

software must read the FIQ status registers of both VIC0 and VIC1 in order to determine the

source of the FIQ interrupt.

When the interrupt flag is cleared in the peripheral(s) that generated the interrupt, the VIC

then will stop asserting the FIQ interrupt to CPU and the flag will be cleared in the VIC FIQ

status register.

1.2.3

IRQ interrupt management

There are two possible ways for handling IRQ interrupts in the VIC:

1.

Vectored handling

2.

Simple (Non vectored) handling

Vectored handling ensures the best interrupt latency because it takes advantage of the

vectored support in the VIC.

Simple handling does not use the hardware priority management of the VIC, but it uses a

software priority management. Although this method increases the interrupt latency, it can

be useful in special cases where a VIC1 interrupt has to be configured with a higher priority

level than a VIC0 interrupt, this is not possible when using the hardware priority

management due to the hardwired priority between VIC0 and VIC1 (see Section 1.2.1).

Vectored handling of IRQ interrupts

When an IRQ interrupt from VIC0 or from VIC1 occurs, then depending on its priority level,

two cases are possible:

– If the interrupt has a lower priority than the current interrupt being processed, then it

remains pending in the VIC until it becomes the higher priority interrupt.

– If the interrupt has the highest priority level then the VIC0 Vector Address register

VIC0_VAR will be loaded with the address of the interrupt service routine and an IRQ

interrupt will be signalled to CPU.

Note:

The VIC0_VAR will be loaded with the ISR address of the interrupt independently from the

origin of the interrupt either from VIC0 or from VIC1.

The vectored flow for handling an IRQ interrupt is the following: