AN2682 - Application note

CPLD design

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CPLD design

The CLPD design is based on the MAX3000A 32 macrocell device shown in Figure 3.

Figure 3.

MAX3000A CPLD pin description

The CPLD bridge is intended to function as the master for both SPI and I2S devices. Since

the SPI peripheral is bidirectional, two I2S devices can be connected at once, as long as

they have the same SCK clock (some I2S devices are also bidirectional).

When a single device is interfaced to the microcontroller, the unused direction logic can

simply be ignored and has no effect on the interface. The CPLD bridge connections with the

STR7/9 MCU and the I2S audio device(s) are illustrated in Figure 4.

Figure 4.

SPI to I2S CPLD bridge connections

The Conf pin is used only in configuration mode. In communication mode, it can be used for

any other application purpose.

MOSI

MISO

SCLK

CLK

Start

Conf

SDo

SDi

WSo

WSi

SCK

STR7/9

CPLD

interface

Audio

I2S

device(s)

PWM OCMPA

GPIO

GPIO

GPIO/AF

GPIO/AF

AF

MCU