AN2691 datasheet(7/10 Pages) STMICROELECTRONICS

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AN2691

External RPD circuitry examples

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2.1.3

RC network sizing

To calculate the external C value, we will suppose that a time T is required to stabilize the

oscillator and PLL circuit. Regarding a generic inverter I/O characteristic, the output level Vo

of that inverter can be considered high as long as the input level Vi is higher than its VIHmin

(see Figure 4: Generic inverter I/O characteristics).

Figure 4.

Generic inverter I/O characteristics

In the same way, as long as the RPD voltage is higher than VIH1, CPU and peripherals are

not fed with any clock (Figure 2: Simplified power down exit circuitry). Therefore, the

capacitor value must be chosen to maintain the voltage above VIH1 for at least the time

Trestart required by the PLL and oscillator (also the input hysteresis on the RPD pin (VHYS4)

must be considered).

Using the simple formula that controls the discharge of capacitor C, we obtain:

where Ipulldown is the current that flows internally through the weak pull-down.

Supposing VDD = 5 V, since (see product datasheet) VIH1 = 3.5 V, VHYS4min = 500 mV,

VHYS4max = 1500 mV, Ipulldown = 200 µA and Trestart = 10.2 ms (crystal oscillator + PLL),

it follows that:

As during reset a pull-down is activated on the RPD pin, the capacitor C will be discharged.

Subsequently the voltage will drop, causing the RPD pin to be seen at a low level. Therefore,

an asynchronous reset will be detected.

VOHmin

VOLmax

VILmax

VIHmin

Ipulldown

Trestart

⋅

VDD

VIH1 VHYS4

–

()

–

-----------------------------------------------------------------

Ipulldown

Trestart

⋅

VDD

VIH1 VHYS4min

–

()

–

----------------------------------------------------------------------------

200

–

10 2

–

⋅⋅

⋅

----------------------------------------------------------------------

µF

∼

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