DocID15287 Rev 9

5/41

AN2867

List of figures

5

List of figures

Figure 1.

Quartz crystal model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Impedance representation in the frequency domain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

I-V curve of a dipole showing a negative transresistance area (in purple) . . . . . . . . . . . . . . 9

Figure 4.

Block diagram of a typical oscillation loop based on a crystal resonator . . . . . . . . . . . . . . 10

Figure 5.

Pierce-oscillator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6.

Inverter transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7.

Current drive measurement with a current probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8.

Negative resistance measurement methodology description . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9.

Classification of low-speed crystal resonators available on the market . . . . . . . . . . . . . . . 20

Figure 10.

Recommended layout for an oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11.

PCB with separated GND plane and guard ring around the oscillator . . . . . . . . . . . . . . . . 32

Figure 12.

GND plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 13.

Signals around the oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 14.

Preliminary design (PCB design guidelines not respected) . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 15.

Final design (all design guidelines have been respected) . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16.

GND plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17.

Top layer view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 18.

PCB guidelines not respected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 19.

PCB guidelines respected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36