AN2945

Core

Doc ID 15468

5/18

1

Core

The STM8™ CPU is a proprietary architecture that maintains the legacy of the previous ST7

core while being a breakthrough in terms of 8-bit CPU efficiency and code density. The

from the complete ecosystem of development tools and software solutions associated with

ARM processors. Although they may be perceived as radically different, these two

processors indeed share many architectural similarities summarized in Table 1.

Both are based on the Harvard architecture. They have 3-stage pipelined execution that

minimizes the execution time, a clock speed up to 24 MHz for the STM8S and up to 72 MHz

for the STM32 family.

They are devised to be highly energy efficient, with several low power modes, and they

benefit from memory interfaces wider than the average instruction length (32- and 64-bit

wide busses, respectively). This minimizes the number of accesses to the memory bus and

thus the consumption related to address bus toggling and non-volatile memory read

accesses. Interrupt tail chaining and the Halt/Sleep on exit modes also help avoiding

unnecessary stack accesses.

Finally, in terms of code density, both have excellent results, owing to the 8-bit CISC

instruction set for the STM8S family and, to the 16-bit Thumb-2 mode introduced by the

Cortex core for the STM32 family.

This short comparison demonstrates that both processors are state-of-the-art in terms of

micro-architectural features. The STM8 is at the level of legacy of 16-bit processors, and the

Cortex-M3 meets the requirements of applications currently using 32-bit down to mid/high-

end 16-bit MCUs. The combination of the STM8 and STM32 therefore establishes a

performance continuum, which is now also supported at tool levels by a third party offering a

unified development platform for both product lines.

Table 1.

STM8 and STM32: core comparison

STM8

Cortex-M3

Data path

8-bit

32-bit

Drhystone MIPS (0WS)

0.29 DMIPS

1.22 DMIPS

Architecture

Harvard

Harvard

Pipeline

Yes, three-stage

Yes, three-stage

Instruction set

CISC

RISC

Program bus data width

32-bit

32-bit

Prefetch buffer

Yes, 2 × 32-bit, internal

Yes, 2 × 64-bit, in memory interface

Average instruction size

2 bytes

2 bytes

Interrupt type

Latency

Vectorized

9 cycles, tail chaining supported

Vectorized

12 cycles, tail chaining supported

Low power modes

Slow, Wait for Event or interrupts,

Halt, Halt on exit

Slow, Sleep (Wait for event or

interrupt), Sleep on exit, Deep sleep

Debug interface

1-wire (SWIM)

2-wires or legacy JTAG