AN3002

M24LRxx’s conditional memory access

Doc ID 15912 Rev 2

13/22

4

M24LRxx’s conditional memory access

authorizes it. This feature provides an easy way of sharing data between contact access

reader/writer.

Figure 5.

M24LRxx memory sharing concept

4.1

M24LRxx’s conditional memory access using passwords

4.1.1

In the following example, the initial setting of the M24LRxx is described in the Table 8 and

Table 9 below. Sectors 1 and 2 in the memory are protected against write accesses: bits b1

and b2 in the I2C_Write lock bit area are set to 1.

I2C access

M24LRxx

RF access

memory

Data access

in read and

write modes

0x12345678

01010

0x12345678

01010

Data access

in write mode

0x12345678

0x12345678

Data access

in read mode

01010

01010

01010

01010

Data access

in read mode

Data access

in write mode

Data access

in read and

write modes

ai17125

Table 8.

I2C_Write_Lock bit

Bits[31:24]

Bits[23:16]

Bits[15:8]

Bits[7:0]

2048

0000 0000b

0000 0000b

0000 0000b

0000 0110b

2052

0000 0000b

0000 0000b

0000 0000b

0000 0000b