AN3070

DE signal timing constraint

Doc ID 16312 Rev 1

5/12

1

DE signal timing constraint

For serial half-duplex communication protocols like RS-485 & IO-Link, the master needs to

generate a direction signal to control the transceiver (PHY). This signal informs the PHY if it

must act in send or receive mode.

The timing of this control is critical, especially when switching from the send to the receive

mode, as the application has to make sure that the device is in reception mode before data

are sent by the other entity.

The master has to free the Tx/Rx line in no more than a bit time, otherwise there is a

collision with the slave response. So the DE signal has to switch from high to low level within

the bit time that follows the last bit of the last byte sent by the master.

Figure 1.

DE timing constraint

The master should be able to guarantee the timing of the DE signal (imposed by the RS-485

& IO-Link specifications). The DE signal is managed by a GPIO.

Note that in this application note, the DE signal is emulated by GPIO port C pin 6 (PC6),

however any GPIO could be used.

Master request

Slave response

t

C/Q line

DE (Driver Enable)

ai17356