AN3250

Designing an M24LR64-R multi-bank application

Doc ID 17761 Rev 1

5/16

M24LR64-R #2 (Bank 2)

M24LR64-R #3 (Bank 3)

To emulate a 256-Kbit device using four M24LR64-R devices, the 256 Kbits are dispatched

as follows:

●

M24LR64 #0 will store the 1st block of 64-Kbit EEPROM memory area.

●

M24LR64 #1 will store the 2nd block of 64-Kbit EEPROM memory area.

●

M24LR64 #2 will store the 3rd block of 64-Kbit EEPROM memory area.

●

M24LR64 #3 will store the 4th block of 64-Kbit EEPROM memory area.

2.2

Connecting several M24LR64-R devices on the same

inductive antenna

The RF interface of M24LR64 devices is based on a passive RFID technology operating at

13.56 MHz in compliance with ISO/IEC 15693 standards. The basic principles of this RF

technology and antenna design considerations are described in the following two application

notes:

●

AN2972: Designing an antenna for the M24LR64-R dual interface I²C/RFID device

●

AN3178: Using a surface mount inductor as an M24LRxx antenna

The basic principle of the M24LR64-R's antenna is very simple; the external antenna

MHz. This is because ISO/IEC 15693 RFID readers operate in the 13.56 MHz high

frequency band.

In this reference design, we connect a number n of M24LR64-R devices in parallel on the

the tuning capacitance of a single M24LR64-R.

Device type identifier

Chip Enable address

RW

b7

b6

b5

b4

b3

b2

b1

b0

Device Select code

1010

E2

10

RW

Device type identifier

Chip Enable address

RW

b7

b6

b5

b4

b3

b2

b1

b0

Device Select code

1010

E2

11

RW

f

TUNING

1

2

Π

L

INDUCTOR

C

TUNINGIC

•

•

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