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AN3265 数据表(PDF) 13 Page - STMicroelectronics |
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AN3265 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 19 page ![]() AN3265 Software description Doc ID 17860 Rev 1 13/19 triggers an interrupt and launches the CLK_IRQHandler() routine. CSS_flag is set and the application goes to step 3 (SystemState = 2). 3. SystemState = 2 LD3 blinks slower than in state 2 since the master clock source is fHSI/8. Pressing Button1 triggers an interrupt. The ButtonPressed flag is set by the PortB_IRQHandler() routine, and a software reset is generated to disable the CSS (see Section 2.3.2: Interrupt function flowcharts). SystemState value is saved in the data EEPROM before the reset occurs. 4. SystemState = 3 LD4 blinks. The HSE clock is set to the master clock source and the CSS is disabled to demonstrate how the IWDG can be used to solve microcontroller hardware or software failures. Pressing Button2 for longer than the IWDG refresh window (1.02 s) stops the application by simulating a master clock source failure. After the refresh period has elapsed, the IWDG resets the STM8S105C6T6, and the application is re-initialized (SystemState = 0). Figure 5 shows the flowchart of the State_Machine() function. |
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