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PM0020 数据表(PDF) 39 Page - STMicroelectronics |
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PM0020 数据表(HTML) 39 Page - STMicroelectronics |
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39 / 87 page  PM00020 STR91xFA Flash memory 39/87 1.15.7 BC fifth entry target address register (FMI_BCE5ADDR) Address Offset: 5400 0020h Reset value: 0000 0006h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BCE5ADDR[23:16] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9876543210 BCEADDR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, always read as 0 Bits 23:0 BCE5ADDR[23:0]: Branch Cache Fifth Entry Target Address These bits are set and cleared by software. They define the target address of the BC 5th entry, provided to implement interrupt (IRQ) mode or any “special” branch not subject to the LRU algorithm. Defaults to 0x00000006 at reset i.e. IRQ exception at 0x18. |
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