PM0064

Programming sequence

Doc ID 16274 Rev 3

9/13

Note:

The ‘Low’ level of Steps 6 and 7 during programming are not absolutely mandatory. They

could be ‘High’ if it is easier for the electronic command; provided they have the correct level

for the next state transition.

7.

CS = LOW

CS = 0 to prevent false signal when VREG is raised later on.

8.

VREG = VDD

Connect VREG to VDD (6.7 V).

9.

Wait 200 ms.

Allow time for option programming process.

10.

VREG release

Disconnect VREG from VDD.

11.

Wait 20 ms.

Allow time for VREG capacitor to discharge.

Table 5.

Option programming (State_4) (continued)

Step

Action

Explanation

Table 6.

Option programming (State_6)

Step

Action

Explanation

1.

CX - 1 double clock

Clock the IC into State_6.

2.

CS = HIGH

CS = 1 required to remain in State_6.

3.

CX - 1 double clock

Signal for IC to program options.

4.

CX = LOW

CX = 0 to prevent false signal when VREG is raised later on.

5.

CS = LOW

CS = 0 to prevent false signal when VREG is raised later on.

6.

VREG = VDD

Connect VREG to VDD (6.7 V).

7.

Wait 200ms

Allow time for option programming process.

8.

VREG release

VDD = 5.0 V

Disconnect VREG from VDD and decrease VDD voltage back to

5V.

9.

Wait 20 ms

Allow time for VREG capacitor to discharge.

10.

CX - 1 double clock

Clock the IC into State_7.