PD16640C_15 datasheet(13/18 Pages) RENESAS

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Data Sheet S11269EJ1V1DS00

µµµµ PD16640C

Switching Characteristics (TA =

−−−−10 to +75 °°°°C, VDD1 = 3.3 V ±±±± 0.3 V, VDD2 = 3.3 V ±±±± 0.3 V or 5.0 V ±±±± 0.5 V,

VSS1 = VSS2 = 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Start pulse delay time

tPLH1

CL = 15 pF

tPHL1

712

Driver output delay time

tPLH21

VDD2=3.3 V

VO:0.1 V

2.6

µ s

tPLH31

2 k

Ω +75 pF x 2

→3.2 V

3.0

µ s

tPHL21

VO:3.2 V

2.4

µ s

tPHL31

→0.1 V

3.2

µ s

Driver output delay time

tPLH22

VDD2=5.0 V

VO:0.1 V

2.2

µ s

tPLH32

2 k

Ω +75 pF x 2

→4.9 V

2.9

µ s

tPHL22

VO:4.9 V

2.6

µ s

tPHL32

→0.1 V

3.6

µ s

Input capacitance

CI1

STHR(STHL), TA=25

°C10

CI2

V0-V10, TA = 25

°C

100

CI3

STHR(STHL), other than V0-V10,

TA=25

°C

Timing Requirements (TA =

−−−−10 to +75 °C, VDD1 = 3.3 V ±±±± 0.3 V, VSS1 = 0 V, tr = tf = 3.0 ns)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Clock pulse width

PWCLK

Clock pulse high period

PWCLK (H)

4ns

Clock pulse low period

PWCLK (L)

4ns

Data setup time

tSETUP1

4ns

Data hold time

tHOLD1

0ns

Start pulse setup time

tSETUP2

4ns

Start pulse hold time

tHOLD2

0ns

INV setup time

tSETUP4

4ns

INV hold time

tHOLD4

0ns

Start pulse low period

tSPL

2CLK

Start pulse rise time

tSPR1

Osel=H

100

CLK

tSPR2

Osel=L

103

CLK

Final data timing

tSETUP3

1CLK

CLK-STB time

tINV

1CLK

STB-CLK time

tLDT

1CLK

Time between STB and start pulse tCLK-STB

CLK

↑→STB↑

7ns

STB-POL time

tSTB-CLK

STB

↑ →CLK↑

7ns

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