UM0629

Overview

Doc ID 15312 Rev 2

5/26

1.4

Hardware layout and configuration

The STM8L101-EVAL evaluation board is designed around the STM8L101K3T6 in an

LQFP32 package.

Figure 2 illustrates the connections between the daughterboard and the peripherals on the

motherboard (LCD, I2C EEPROM, USART, audio and MicroSD card).

Figure 3 and Figure 4 help you to locate these features on the actual evaluation board.

Figure 2.

Hardware block diagram

STM8L1/L2-MB

RS232

transceiver

5V power

jack

3.3V

regulator

LCD

MicroSD card

Level

translator

Audio circuit

BNC connector

I2C EEPROM

SWIM connector

STice connector

Push button

Joystick

LED’s

Potentiometer

RS232

connector

SWIM

ADC

ADC

PWM

USART

Compa

rator

SPI

I2C

Economic

Measurement

BEEP

1.8 to 3.3V

regulator

Bi-color LED

GPIO’s

Extension connector

STM8L1-DB

STM8L1/L2-MB (MB709)

STM8L101

MCU

STM8L1-DB (MB710)

CMP