AN2440

EEPROM with embedded ECCx4 feature

Doc ID 023074 Rev 4

5/13

2

EEPROM with embedded ECCx4 feature

2.1

Memory array architecture

ST EEPROM devices with the ECCx4 feature are organized in pages of 32, 64 128 or 256

bytes (depending on the memory density of the device). Inside a page, the bytes are packed

Figure 4.

Figure 4.

Word of 4 bytes with 6 ECC bits

The memory array represented in Figure 5 shows the memory architecture with embedded

ECCx4. The data entity of the array becomes the [4 data bytes + 6 ECC bits]. ECC bits are

standard non-volatile EEPROM bits.

The ECC bits are linked to the value of the 4 data bytes in the word; each time a data byte is

written inside a word, the corresponding ECC bits are computed and updated. With 6 ECC

bits, only one bit error in the 4 data bytes can be corrected.

Note:

The ECCx4 cannot correct two or more bit errors, however the probability that 2 bits become

The internal data is managed on a word-by-word basis (4 bytes + 6 ECC bits). This internal

management is transparent to the Master bus as the device single byte granularity remains

unchanged.

Figure 5.

Memory array architecture of EEPROMs with embedded ECCx4

a.

A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.

ai13475

8 bits 8 bits 8 bits 8 bits

Col0

6 bits

Col1

Col2

Col3

ECC

Memory array

0000h

0004h

0008h

Word = 4 bytes + 6 ECC bits

ai13483