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AN4206

Debug management

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4.3.1

SWJ debug port pins

Five pins are used as outputs for the SWJ-DP as alternate functions of general-purpose

I/Os (GPIOs). These pins, shown in Table 2, are available on all packages.

4.3.2

Flexible SWJ-DP pin assignment

After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as

dedicated pins immediately usable by the debugger host (note that the trace outputs are not

assigned except if explicitly programmed by the debugger host).

However, some of the JTAG pins shown in Table 3 can be configured to an alternate

function through the GPIOx_AFRx registers.

Table 3 shows the different possibilities to free some pins to be configured alternate

functions.

For more details, see the corresponding STM32F3xx reference manual (RM0316, RM0313,

Table 2. Debug port pin assignment

SWJ-DP pin name

JTAG debug port

SW debug port

Pin

assignment

Type

Description

Type

Debug assignment

JTMS/SWDIO

I

JTAG test mode

selection

I/O

Serial wire data

input/output

PA13

JTCK/SWCLK

I

JTAG test clock

I

Serial wire clock

PA14

JTDI

I

JTAG test data input

-

-

PA15

JTDO/TRACESWO

O

JTAG test data

output

-

TRACESWO if async

trace is enabled

PB3

JNTRST

I

JTAG test nReset

-

-

PB4

Table 3. SWJ I/O pin availability

Available Debug ports

SWJ I/O pin assigned

PA13 /

JTMS/

SWDIO

PA14 /

JTCK/

SWCLK

PA15 /

JTDI

PB3 /

JTDO

PB4/

JNTRST

Full SWJ (JTAG-DP + SW-DP) - reset state

X

X

X

X

X

Full SWJ (JTAG-DP + SW-DP) but without

JNTRST

XX

X

X

JTAG-DP disabled and SW-DP enabled

X

X

JTAG-DP disabled and SW-DP disabled

Free to be configured as alternate functions