DocID027161 Rev 1

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AN4617

Peripheral migration

25

2.3

Memory mapping

The peripheral address mapping has been changed in the F0 series compared to the L0

series. The main change concerns the GPIOs, they are on AHB bus in the F0 series and on

Table 5 provides the peripheral address mapping correspondence between F0 and L0

series (differences between the two series are highlighted with bold type).

Table 5. IP bus mapping cross reference

Peripheral

STM32F0 series

STM32L0 series

Bus

Base address

Bus

Base address

AES

AHB1

NA

AHB

0x40026000

RNG

NA

0x40025000

TSC

0x40024000

0x40024000

CRC

0x40023000

0x40023000

FLITF

0x40022000

0x40022000

RCC

0x40021000

0x40021000

DMA / DMA1

0x40020000

0x40020000

DMA2

0x40020400

NA

GPIOH

AHB2

NA

IOPORT

0x50001C00

GPIOF

0x48001400

NA

GPIOE

0x48001000

0x50001000

GPIOD

0x48000C00

0x50000C00

GPIOC

0x48000800

0x50000800

GPIOB

0x48000400

0x50000400

GPIOA

0x48000000

0x50000000