DocID027369 Rev 1

7/17

AN4646

Peripheral interconnect matrix

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Peripheral interconnect matrix

STM32F401/411 peripherals are interconnected through the peripheral interconnect matrix

that allows to directly connect one peripheral to another without waking up the CPU.

These interconnections can operate in Run, Sleep or Stop modes, depending on

peripherals.

Peripherals that respond to events are referred to as users while peripherals that send

events are referred to as generators.

Users

Generators

Timers

DMA

Analog

TIM 1

TIM 2

TIM 3

TIM 4

TIM 5

TIM 11 DMA1 DMA2

ADC1

Timers

TIM1

-X

X

X

-

-

-

X

X

TIM2

X

-

XXX

-

X

-

X

TIM3

XX

-

X

X

-

X

-

X

TIM4

XX

X

-

X

-

X

-

X

TIM5

X-

X-

-

-

X

-

X

Analog

ADC1

--

---

-

-

X

-

VSENSE

--

---

-

-

-

X

Clocks

LSI

--

--

X

-

-

-

-

LSE

--

--

X

-

-

-

-

RTC

--

--

X

X

-

-

-

CSS

X

-

---

-

-

-

-