DocID027496 Rev 1

13/24

AN4658

Peripheral migration guide

23

2.6

RCC

The main differences related to Reset and Clock Controller in the STM32F446 line vs. the

STM32F429/439 lines are presented in Table 8, where a gray cell indicates that the feature

is not available.

95

NA

FMP2C1

96

NA

FMPI2C1 error

Table 7. Interrupt vector comparison (continued)

Position

STM32F429xx/439xx

STM32F446xx

Table 8. Reset and Clock Controller comparison

RCC

STM32F429xx/439xx

STM32F446xx

AHB

180 MHz

180 MHz

APB2

84 MHz

84 MHz

APB1

42 MHz

42 MHz

PLL

– One clock input divider for

all PLLs (M factor)

– New dedicated clock input

divider for each PLL

– One input clock divider per

PLL that needs to be

configured before enabling

the PLL

System clock (SYSCLK)

HSI/HSE

HSI/HSE

PLL_P

PLL_P

PLL_R

LSE modes

– One LSE mode is

available: low power.

– New LSE modes are available

in STM32446: low power and

high drive.

– User can select the LSE mode

by configuring

RCC_BDCR[LSEMOD] bit

Peripherals clock sources

USB OTG FS / SDIO

(PLL48CLK)

48 MHz from main PLL

(PLLQ clock output)

48 MHz from main PLL

(PLLQ clock output)

-

48 MHz from PLLSAI

(PLLSAIP clock output)

SDIO

PLL48CLK

PLL48CLK

System clock (SYSCLK)

FMPI2C

NA

System clock (SYSCLK)

HSI clock

APB1 clock (PCLK1)