Specifications GAL16V8

14

Note: tcf is a calculated value, derived by subtracting tsu from

the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The

value of tcf is used primarily when calculating the delay from

clocking a register to a combinatorial output (through registered

feedback), as shown above. For example, the timing from clock

to a combinatorial output is equal to tcf + tpd.

Note: fmax with external feedback is calculated from measured

tsu and tco.

Note: fmax with no feedback may be less than 1/(twh + twl). This

is to allow for a clock duty cycle of other than 50%.

REGISTER

LOGIC

ARRAY

CLK

REGISTER

LOGIC

ARRAY

CLK

Test Condition

A

200

Ω

390

Ω

50pF

B

Active High

∞

390

Ω

50pF

Active Low

200

Ω

390

Ω

50pF

C

Active High

∞

390

Ω

5pF

Active Low

200

Ω

390

Ω

5pF

CLK

REGISTER

LOGIC

ARRAY

TEST POINT

C *

L

FROM OUTPUT (O/Q)

UNDER TEST

+5V

Input Pulse Levels

Table 2-0003/16V8

Input Rise

and Fall Times

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to 3.0V

1.5V

1.5V

See figure at right

3-state levels are measured 0.5V from

steady-state active level.

2 – 3ns 10% – 90%

1.5ns 10% – 90%

GAL16V8D-10

(and slower)

GAL16V8D-3/-5/-7

GAL16V8D (except -3) Output Load Conditions (see figure

above)

Switching Test Conditions