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LT1002ACJ 数据表(PDF) 3 Page - Linear Technology |
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LT1002ACJ 数据表(HTML) 3 Page - Linear Technology |
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3 / 16 page  3 LT1002 ELECTRICAL CHARACTERISTICS, I DIVIDUAL A PLIFIERS VS = ±15V, –55°C ≤ TA ≤ 125°C, unless otherwise noted LT1002AM LT1002M SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS VOS Input Offset Voltage Note 1 q 30 150 45 230 µV ∆VOS Average Input Offset Voltage Drift q 0.2 0.9 0.3 1.3 µV/°C ∆Temp IOS Input Offset Current q 0.8 5.6 1.2 8.5 nA IB Input Bias Current q ±1.0 ±6.0 ±1.5 ±9.0 nA AVOL Large Signal Voltage Gain RL ≥ 2kΩ, VO = ±10V q 300 700 200 700 V/mV CMRR Common Mode Rejection Ratio VCM = ±13V q 106 122 104 120 dB PSRR Power Supply Rejection Ratio VS = ±3V to ±18V q 102 117 96 117 dB Input Voltage Range q ±13 ±14 ±13 ±14 V VOUT Output Voltage Swing RL ≥ 2kΩ q ±12.5 ±13.5 ±12.0 ±13.5 V Pd Power Dissipation No load q 55 90 60 100 mW per amplifier LT1002AC LT1002C SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS VOS Input Offset Voltage Note 1 q 20 100 30 160 µV ∆VOS Average Input Offset Voltage Drift q 0.2 0.9 0.3 1.3 µV/°C ∆Temp IOS Input Offset Current q 0.5 4.2 0.6 5.7 nA IB Input Bias Current q ±0.7 ±4.5 ±1.0 ±6.0 nA AVOL Large Signal Voltage Gain RL ≥ 2kΩ, VO = ±10V q 350 750 250 750 V/mV CMRR Common Mode Rejection Ratio VCM = ±13V q 108 124 106 123 dB PSRR Power Supply Rejection Ratio VS = ±3V to ±18V q 105 120 100 120 dB Input Voltage Range q ±13 ±14 ±13 ±14 V VOUT Output Voltage Swing RL ≥ 2kΩ q ±12.5 ±13.8 ±12.5 ±13.8 V Pd Power Dissipation No Load q 50 85 55 90 mW per amplifier VS = ±15V, 0°C ≤ TA ≤ 70°C, unless otherwise noted The q denotes the specifications which apply over the full operating temperature range. For MIL-STD components, please refer to LTC 883C data sheet for test listing and parameters. Note 1: Offset voltage measured with high speed test equipment, approximately 1second after power is applied. Note 2: This parameter is tested on a sample basis only. Note 3: Long Term Input Offset Voltage Stability refers to the averaged trend line of VOS versus Time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 µV. Note 4: Parameter is guaranteed by design. Note 5: 10Hz noise voltage density is sample tested on every lot. Devices 100% tested at 10Hz are available on request. Note 6: The V + supply terminals are completely independent and may be powered by separate supplies if desired (this approach, however, would sacrifice the advantages of the power supply rejection ratio matching). The V – supply terminals are both connected to the common substrate and must be tied to the same voltage. Both V – pins should be used. |
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