10

LT1352/LT1353

mended for applications where DC accuracy must be

maximized. The inputs can withstand differential input

voltages of up to 10V without damage and need no

clamping or source resistance for protection. Differential

inputs generate large supply currents (up to 40mA) as

required for high slew rates. Typically power dissipation

does not significantly increase because of the low duty

cycle of the transient inputs. If the device is used as a

comparator with sustained differential inputs, excessive

power dissipation may result.

Circuit Operation

The LT1352/LT1353 circuit topology is a true voltage

feedback amplifier that has the slewing behavior of a

current feedback amplifier. The operation of the circuit can

be understood by referring to the Simplified Schematic.

The inputs are buffered by complementary NPN and PNP

emitter followers which drive R1, a 1k resistor. The input

voltage appears across the resistor generating currents

which are mirrored into the high impedance node and

form an output stage which buffers the gain node from the

load. The output devices Q19 and Q22 are connected to

form a composite PNP and a composite NPN.

The bandwidth is set by the input resistor and the capaci-

tance on the high impedance node. The slew rate is

determined by the current available to charge the high

impedance node capacitance. This current is the differen-

tial input voltage divided by R1, so the slew rate is

proportional to the input. Highest slew rates are therefore

seen in the lowest gain configurations. For example, a 10V

output step in a gain of 10 has only a 1V input step whereas

the same output step in unity gain has a 10 times greater

input step. The graph Slew Rate vs Input Level illustrates

this relationship. In higher gain configurations the large-

signal performance and the small-signal performance

both look like a single pole response.

network which is bootstrapped across the output stage.

When the amplifier is driving a light load the network has

no effect. When driving a capacitive load (or a low value

resistive load) the network is incompletely bootstrapped

and adds to the compensation at the high impedance

node. The added capacitance slows down the amplifier

and a zero is created by the RC combination, both of which

improve the phase margin. The design ensures that even

for very large load capacitances, the total phase lag can

never exceed 180 degrees (zero phase margin) and the

amplifier remains stable.

Power Dissipation

The LT1352/LT1353 combine high speed and large output

drive in small packages. Because of the wide supply

voltage range, it is possible to exceed the maximum

junction temperature of 150

°C under certain conditions.

follows:

LT1353CS:

Worst-case power dissipation occurs at the maximum

supply current and when the output voltage is at 1/2 of

either supply voltage (or the maximum swing if less than

Example: LT1353 in S14 at 85