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UPD75316B 数据表(PDF) 58 Page - NEC |
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UPD75316B 数据表(HTML) 58 Page - NEC |
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58 / 77 page  58 µPD75312B, 75316B SO output delay time from SCK ↓ 1600 ns 3800 ns VDD = 4.5 to 6.0 V tKCY1/2–50 ns tKCY1/2–150 ns 250 ns 400 ns VDD = 4.5 to 6.0 V 250 ns 1000 ns SERIAL TRANSFER OPERATION 2-wire and 3-wire serial I/O mode (SCK...Internal clock output): (Ta = –40 to +85 °C , VDD = 2.0 to 6.0 V ) SCK cycle time tKCY1 tKSO1 SI setup time (to SCK ↑) SI hold time (from SCK ↑) tKSI1 tSIK1 tKL1 tKH1 SCK high- and low-level width VDD = 4.5 to 6.0 V * RL and CL are SO output line load resistance and load capacitance, respectively. 2-wire and 3-wire serial I/O mode (SCK...External clock input): (Ta = –40 to +85 °C , VDD = 2.0 to 6.0 V ) VDD = 4.5 to 6.0 V 800 ns 3200 ns VDD = 4.5 to 6.0 V 400 ns 1600 ns 100 ns 400 ns VDD = 4.5 to 6.0 V 300 ns 1000 ns SCK cycle time tKCY2 tKL2 tKH2 SI setup time (to SCK ↑) tSIK2 tKSI2 SI hold time (from SCK ↑) tKSO2 SO output delay time from SCK ↓ * RL and CL are SO output line load resistance and load capacitance, respectively. SCK high- and low-level widths PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT RL = 1 k Ω, CL = 100 pF* RL = 1 k Ω, CL = 100 pF* |
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