LT1776CS8 datasheet(13/20 Pages) LINER

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LT1776

APPLICATIONS INFORMATION

The high speed switching current path is shown schemati-

cally in Figure 3. Minimum lead length in these paths is

essential to ensure clean switching and minimal EMI. The

paths containing the input capacitor, output switch and

output diode are the only ones containing nanosecond rise

and fall times. Keep these paths as short as possible.

As an example, assume that the capacitance between the

VSW node and a high impedance pin node is 0.1pF, and

further assume that the high impedance node in question

exhibits a capacitance of 1pF to ground. Due to the high

dV/dt, large excursion behavior of the VSW node, this will

couple a nearly 4V transient to the high impedance pin,

causing abnormal operation. (This assumes the “typical”

40VIN to 5VOUT application.) An explicit 100pF capacitor

added to the node will reduce the amplitude of the distur-

bance to more like 50mV (although settling time will

increase).

Specific pin recommendations are as follows:

SHDN: If unused, add a 100pF capacitor to ground.

SYNC: Ground if unused.

VC: Add a capacitor directly to ground in addition to the

explicit compensation network. A value of one-tenth of

the main compensation capacitor is recommended, up

to a maximum of 100pF.

FB: Assuming the VC pin is handled properly, this pin

usually requires no explicit capacitor of its own, but

keep this node physically small to minimize stray

capacitance.

LT1776

VSW

VIN

VOUT

VIN

1776 F03

Figure 3. High Speed Current Switching Paths

Additionally, it is possible for the LT1776 to cause EMI

problems by “coupling to itself”. Specifically, this can

occur if the VSW pin is allowed to capacitively couple in an

uncontrolled manner to the part’s high impedance nodes,

i.e., SHDN, SYNC, VC and FB. This can cause erratic

operation such as odd/even cycle behavior, pulse width

“nervousness”, improper output voltage and/or prema-

ture current limit action.

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