LTC1093ACN datasheet(21/32 Pages) LINER

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LTC1091/LTC1092

LTC1093/LTC1094

APPLICATI

I FOR ATIO

3. Analog Inputs

Because of the capacitive redistribution A/D conversion

techniques used, the analog inputs of the LTC1091/

LTC1092/LTC1093/LTC1094 have capacitive switching

input current spikes. These current spikes settle quickly

and do not cause a problem. However, if large source

resistances are used or if slow settling op amps drive the

inputs, care must be taken to ensure that the transients

caused by the current spikes settle completely before the

conversion begins.

Source Resistance

The analog inputs of the LTC1091/LTC1092/LTC1093/

LTC1094 look like a 60pF capacitor (CIN) in series with a

500

Ω resistor (RON) as shown in Figure 7. CIN gets

switched between the selected “+” and “–” inputs once

during each conversion cycle. Large external source resis-

tors and capacitances will slow the settling of the inputs. It

is important that the overall RC time constants be short

enough to allow the analog inputs to completely settle

within the allowed time.

“+” Input Settling

This input capacitor is switched onto the “+” input during

the sample phase (tSMPL, see Figure 8). The sample phase

is the 1 1/2 CLK cycles before the conversion starts. The

voltage on the “+” input must settle completely within this

sample time. Minimizing RSOURCE+ and C1 will improve

the input settling time. If large “+” input source resistance

must be used, the sample time can be increased by using

a slower CLK frequency. With the minimum possible

sample time of 3

µs, RSOURCE+ < 2k and C1 < 20pF will

provide adequate settling.

Figure 5. Poor VCC Bypassing.

Noise and Ripple Can Cause A/D Errors

µs/DIV

1091-4 F05

0.5mV/DIV

Figure 6. Good VCC Bypassing Keeps

Noise and Ripple on VCC Below 1mV

0.5mV/DIV

µs/DIV

1091-4 F06

3RD CLK

↑

RON = 500Ω

4TH CLK

↓

CIN =

60pF

LTC1091

“+”

INPUT

RSOURCE+

VIN+

“–”

INPUT

RSOURCE–

VIN–

LTC091-4 F07

Figure 7. Analog Input Equivalent Circuit

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