7

LTC1152

Compensation/Bandwidth Limiting

The LTC1152 is unity-gain stable with capacitive loads up

to 1000pF. Larger capacitive loads can be driven by

externally compensating the LTC1152. Adding 1000pF

between COMP (pin 5) and OUT (pin 6) allows capacitive

loading of up to 1

µF; 0.1µF between pins 5 and 6 allows the

LTC1152 to drive infinite capacitive load (Figure 3).

1

2

3

4

8

7

6

5

OUTPUT

*OPTIONAL DIODES TO PREVENT

1N4148*

1152 F03

1N4148*

LTC1152

Figure 3. Output Compensation Connection

Large compensation capacitors can also be used to limit

the bandwidth of the LTC1152. With 0.1

µF from pin 5 to

pin 6, the LTC1152’s gain-bandwidth product is reduced

from 700kHz to around 200Hz. Note that compensation

capacitors greater than 1

µF can cause latch-up under

severe output fault conditions; this can be prevented by

clamping pin 5 to each supply with standard signal diodes,

as shown in Figure 3.

Shutdown

The LTC1152 includes a shutdown pin (pin 1). When this

1

µA pull-up keeps the pin high if it is left floating. When pin

1 is pulled low, the part enters shutdown mode; supply

current drops to 1

µA, all internal clocking stops and the

output enters a high impedance state. During shutdown

When pin 1 is brought high again, about 10

µs will elapse

before the charge pump regains full voltage. During this

time the LTC1152 will operate normally, but the input CMR

running from the same supply as the LTC1152. Addition-

ally, the input trip levels allow ground referenced CMOS

logic signals to interface directly to pin 1 when the LTC1152

is running from

±5V or ±3V supplies. The internal 1µA

pull-up also allows pin 1 to interface with open-collector/

open-drain devices or discrete transistors.

The high impedance output in shutdown allows several

LTC1152s to be connected together as a MUX, with their

outputs tied in parallel and the active channel selected by

using the shutdown pins. Deselected (shutdown) chan-

nels will go to high impedance at the outputs, preventing

them from fighting with the active channel. This works

best when the individual LTC1152s are connected in

noninverting feedback configurations to prevent the feed-

back resistors from passing signals through deselected

channels. See the Typical Applications section for a circuit

example.

Zero-Drift Operation

The LTC1152 is a zero-drift op amp. Like other LTC zero-

drift op amps, it features virtually error-free DC perfor-

mance, very little drift over time and temperature, and very

low noise at low frequencies. The internal nulling clock

runs at about 2.3kHz (the charge pump frequency of

4.7MHz divided by 2048) and is synchronized to the

internal charge pump to prevent beat frequencies from

appearing at the output. The self-nulling circuit constantly

corrects the input offset voltage, keeping it typically below

±1µV over the entire input common-mode range. This has

the added benefit of providing exceptional CMRR and

PSRR at low frequencies––far better than competing rail-

to-rail op amps.

Because it uses a sampling front end, the LTC1152 will

exhibit aliasing behavior and clock noise at frequencies

near the internal 2.3kHz sampling frequency. The LTC1152

includes an internal anti-aliasing circuit to keep these error

terms to a minimum. As a rule, alias frequencies will be

LTC1152 circuit. Clock noise is also dependent on closed-

loop gain; it will generally consist of spikes of about 100

µV

in amplitude, input referred. In general, these error terms

are too small to affect most applications. For a more

detailed explanation of zero-drift amplifier behavior, see

the LTC1051/LTC1053 data sheet.

S

APPLICATI

I FOR ATIO

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.