4

LTC1156

I

DAGRA

BLOCK

GATE CHARGE

AND DISCHARGE

CONTROL LOGIC

COMP

LOW STANDBY

CURRENT

REGULATOR

TTL-TO-CMOS

CONVERTER

100mV

REFERENCE

VOLTAGE

REGULATORS

INPUT

LATCH

OSCILLATOR

AND CHARGE

PUMP

FAST/SLOW

GATE CHARGE

LOGIC

ANALOG SECTION

IN

GND

ANALOG

DIGITAL

10

µs

DELAY

GATE

DRAIN

SENSE

ONE

SHOT

R

S

1156 BD

CC

HARA TERISTICS

A

TYPICALPERFOR

CE

SUPPLY VOLTAGE (V)

0

0

100

300

400

500

1000

700

5

10

1156 G07

200

800

900

600

15

20

SUPPLY VOLTAGE (V)

0

0

5

15

20

25

50

35

5

10

1156 G08

10

40

45

30

15

20

SUPPLY VOLTAGE (V)

0

0

5

15

20

25

50

35

5

10

1156 G09

10

40

45

30

15

20

NO EXTERNAL DELAY

Short Circuit Turn-OFF Delay Time

Turn-OFF Time

Turn-ON Time

ATIO

OPER

The LTC1156 contains four independent power MOSFET

gate drivers and protection circuits (refer to the Block

Diagram for detail). Each section of LTC1156 consists of

the following functional blocks:

TTL and CMOS Compatible Inputs

Each driver input has been designed to accommodate a

wide range of logic families. The input threshold is set at

1.3V with approximately 100mV of hysteresis.