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LTC1098ACN8 数据表(PDF) 3 Page - Linear Technology

部件名 LTC1098ACN8
功能描述  Micropower Sampling 8-Bit Serial I/O A/D Converters
PDF  28 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC1098ACN8 数据表(HTML) 3 Page - Linear Technology

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LTC1096/LTC1096L
LTC1098/LTC1098L
RECO
E DED OPERATI G CO DITIO S
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
Supply Voltage
2.65
4.0
V
fCLK
Clock Frequency
VCC = 2.65V
25
250
kHz
tCYC
Total Cycle Time
LTC1096L, fCLK = 250kHz
58
µs
LTC1098L, fCLK = 250kHz
58
µs
thDI
Hold Time, DIN After CLK
↑
VCC = 2.65V
450
ns
tsuCS
Setup Time CS
↓ Before First CLK↑ (See Operating Sequence)
VCC = 2.65V, LTC1096L
1
µs
VCC = 2.65V, LTC1098L
1
µs
tWAKEUP
Wake-Up Time CS
↓ Before First CLK↓ After First CLK↑
VCC = 2.65V, LTC1096L
10
µs
(See Figure 1, LTC1096L Operating Sequence)
Wake-Up Time CS
↓ Before MSBF Bit CLK↓
VCC = 2.65V, LTC1098L
10
µs
(See Figure 2, LTC1098L Operating Sequence)
tsuDI
Setup Time, DIN Stable Before CLK↑
VCC = 2.65V
1
µs
tWHCLK
CLK High Time
VCC = 2.65V
1.6
µs
tWLCLK
CLK Low Time
VCC = 2.65V
1.6
µs
tWHCS
CS High Time Between Data Transfer Cycles
VCC = 2.65V
2
µs
tWLCS
CS Low Time During Data Transfer
LTC1096L, fCLK = 250kHz
56
µs
LTC1098L, fCLK = 250kHz
56
µs
LTC1096/LTC1098
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tWLCLK
CLK Low Time
VCC = 5V
0.8
µs
tWHCS
CS High Time Between Data Transfer Cycles
VCC = 5V
1
µs
tWLCS
CS Low Time During Data Transfer
LTC1096, fCLK = 500kHz
28
µs
LTC1098, fCLK = 500kHz
28
µs
VCC = 3V Operation
fCLK
Clock Frequency
VCC = 3V
25
250
kHz
tCYC
Total Cycle Time
LTC1096, fCLK = 250kHz
58
µs
LTC1098, fCLK = 250kHz
58
µs
thDI
Hold Time, DIN After CLK
↑
VCC = 3V
450
ns
tsuCS
Setup Time CS
↓ Before First CLK↑ (See Operating Sequence)
VCC = 3V, LTC1096
1
µs
VCC = 3V, LTC1098
1
µs
tWAKEUP
Wake-Up Time CS
↓ Before First CLK↓ After First CLK↑
VCC = 3V, LTC1096
10
µs
(See Figure 1 LTC1096 Operating Sequence)
Wake-Up Time CS
↓ Before MSBF Bit CLK↓
VCC = 3V, LTC1098
10
µs
(See Figure 2 LTC1098 Operating Sequence)
tsuDI
Setup Time, DIN Stable Before CLK↑
VCC = 3V
1
µs
tWHCLK
CLK High Time
VCC = 3V
1.6
µs
tWLCLK
CLK Low Time
VCC = 3V
1.6
µs
tWHCS
CS High Time Between Data Transfer Cycles
VCC = 3V
2
µs
tWLCS
CS Low Time During Data Transfer
LTC1096, fCLK = 250kHz
56
µs
LTC1098, fCLK = 250kHz
56
µs
LTC1096L/LTC1098L



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