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UPD75P0076 数据表(PDF) 45 Page - NEC |
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UPD75P0076 数据表(HTML) 45 Page - NEC |
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45 / 62 page ![]() µPD75P0076 45 DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85˚C) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Release signal set time tSREL 0 µs Oscillation stabilization tWAIT Release by RESET 215/fX ms wait timeNote 1 Release by interrupt request Note 2 ms Notes 1. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the oscillation start. 2. Depends on the basic interval timer mode register (BTM) settings (See the table below). BTM3 BTM2 BTM1 BTM0 Wait time fx = at 4.19 MHz fx = at 6.0 MHz — 000 220/fx (approx. 250 ms) 220/fx (approx. 175 ms) — 011 217/fx (approx. 31.3 ms) 217/fx (approx. 21.8 ms) — 101 215/fx (approx. 7.81 ms) 215/fx (approx. 5.46 ms) — 111 213/fx (approx. 1.95 ms) 213/fx (approx. 1.37 ms) |
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