6

LTC1264

PI FU CTIO S

CLK (Pin 18): Clock Input Pin. Any TTL or CMOS clock

source with a square wave output and 50% duty cycle

(

±10%) is an adequate clock source for the device. The

power supply for the clock source should not be the filter’s

power supply. The analog ground for the filter should be

connected to clock’s ground at a single point only. Table

1 shows the clock’s low and high level threshold values for

a dual or single supply operation.

Table 1. Clock Source High and Low Threshold Levels

POWER SUPPLY

HIGH LEVEL

LOW LEVEL

Dual Supply =

±7.5V

≥ 2.18V

≤ 0.5V

Dual Supply =

±5V

≥ 1.45V

≤ 0.5V

Dual Supply =

±2.5V

≥ 0.73V

≤ –2.0V

Single Supply = 12V

≥ 7.80V

≤ 6.5V

Single Supply = 5V

≥ 1.45V

≤ 0.5V

A pulse generator can be used as a clock source provided

the high level on-time is greater than 0.2

µs.Sinewavesare

not recommended for clock input frequencies less than

100kHz, since excessively slow clock rise or fall times

generate internal clock jitter (maximum clock rise or fall

time

≤1µs). The clock signal should be routed from the

right side of the IC package and perpendicular to it to avoid

coupling to any input or output analog signal path. A 200

Ω

resistor between clock source and Pin 11 will slow down

the rise and fall times of the clock to further reduce charge

coupling (Figures 1 and 2).

HPB/NB, BPB, LPB, LPA, BPA, HPA, HPD, BPD, LPD,

LPC, BPC, HPC/NC (Pins 2, 3, 4, 9, 10, 11, 14, 15, 16,

21, 22, 23): Output Pins. Each 2nd order section of the

LTC1264 has three outputs which typically source 3mA

and sink 1mA. Driving coaxial cables or resistive loads less

than 20k will degrade the total harmonic distortion perfor-

mance of any filter design. When evaluating the distortion

or noise performance of a particular filter design imple-

mented with an LTC1264, the final output of the filter

should be buffered with a wideband noninverting high

slew rate amplifier (Figure 3).

Figure 3. Wideband Buffer

–

+

LT1224

5k

1264 F03

INV B, INV A, INV D, INV C (Pins 1, 12, 13, 24): Inverting

Input Pins. These pins are the high impedance inverting

inputs of internal op amps and they are susceptible to stray

capacitive connections to low impedance signal outputs

and power supply lines.

SB, SA, SD, SC (Pins 5, 8, 17, 20): Summing Input Pins.

The summing pins connections determine the circuit

topology (mode) of each 2nd order section. Please refer to

Modes of Operation.

Please refer to the Maximum Frequency of Operation

paragraph under Applications Information for a guide to

Mode 1b

Mode 1b is derived from Mode 1. In Mode 1b (Figure 5) two

additional resistors R5 and R6 are added to alternate the

amount of voltage fed back from the lowpass output into

the input of the SA (SB, SC or SD) switched-capacitor

summer. This allows the filter’s clock-to-center frequency

ratio to be adjusted beyond 20:1. Mode 1b maintains the

speed advantages of Mode 1 and should be considered an

ODES OF OPERATIO

For the definition of filter functions please refer to the

LTC1060 data sheet.

Mode 1

In Mode 1, the ratio of the external clock frequency to the

center frequency of each 2nd order section is internally

fixed at 20:1. Figure 4 illustrates Mode 1 providing 2nd

order notch, lowpass, and bandpass outputs. Mode 1 can

be used to make high order Butterworth lowpass filters; it

can also be used to make low Q notches and for cascading

2nd order bandpass functions tuned at the same center

frequency. Mode 1 is faster than Mode 3.