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LTC1266CS 数据表(PDF) 17 Page - Linear Technology |
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LTC1266CS 数据表(HTML) 17 Page - Linear Technology |
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17 / 20 page ![]() 17 LTC1266 LTC1266-3.3/LTC1266-5 APPLICATIO S I FOR ATIO times helpful in eliminating instabilities at high input voltage and high output loads. 6. Is the Shutdown (Pin 11) actively pulled to ground during normal operation? The Shutdown pin is high impedance and must not be allowed to float. The Select (Pins 3 and 4) are also high impedance and must be tied high or low depending on the application. 3. Are the Sense – and Sense + leads routed together with minimum PC trace spacing? The 1000pF capacitor between Pins 8 and 9 should be as close as possible to the LTC1266. 4. Does the (+) plate of CIN connect to the source of the topside MOSFET as closely as possible? This capacitor provides the AC current to the topside MOSFET. 5. A 0.1 µF to 1µF decoupling capacitor connected be- tween VIN (Pin 5) and ground is optional, but is some- TYPICAL APPLICATIO S (Layout Assist Schematics) Figure 11. Low Dropout, 3.3V/3A High Efficiency Regulator 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 TDRIVE PWR VIN PINV BINH VIN CT ITH SENSE– BDRIVE PGND LBOUT LBIN SGND SHDN NC SENSE+ LTC1266-3.3 1 µF 1000pF SHUTDOWN BINH RSENSE 0.033 Ω L* 10 µH Si9410DY D1 MBRS140T3 Si9430DY + CIN 100 µF 25V VIN ≈3.9V TO 18V (VIN(MIN) = 3.5V IF ILOAD < 0.8A) COUT 220 µF 10V 2 × VOUT 3.3V 3A CC 3300pF RC 1k CT 220pF LTC1266 • F11 DALE LPT4545-A001 COILTRONICS CTX10-4 * |
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