13

LTC1279

S

APPLICATI

I FOR ATIO

be located as close to the pins as possible. The traces

connecting the pins and the bypass capacitors must be

kept short and should be made as wide as possible.

from AGND (pin 3) should be kept as short as possible to

minimize input noise coupling. In applications where this

is not possible, a shielded cable between the signal source

and ADC is recommended. Also, since any potential differ-

ence in grounds between the signal source and ADC

appears as an error voltage in series with the input signal,

attention should be paid to reducing the ground circuit

impedances as much as possible.

A single point analog ground, separate from the logic

system ground, should be established with an analog

ground plane at pin 3 (AGND) or as close as possible to the

ADC. Pin 12 (DGND) and all other analog grounds should

be connected to this single analog ground point. No other

digital grounds should be connected to this analog ground

point. Low impedance analog and digital power supply

common returns are essential to low noise operation of

the ADC and the foil width for these tracks should be as

wide as possible. In applications where the ADC data

outputs and control signals are connected to a continu-

ously active microprocessor bus, it is possible to get

errors in conversion results. These errors are due to

feedthrough from the microprocessor to the successive

approximation comparator. The problem can be elimi-

nated by forcing the microprocessor into a WAIT state

during conversion or by using three-state buffers to iso-

late the ADC data bus.

DIGITAL INTERFACE

The A/D converter is designed to interface with micropro-

cessors as a memory mapped device. The CS and RD

control inputs are common to all peripheral memory interfac-

ing. A separate CONVST is used to initiate a conversion.

Internal Clock

The A/D converter has an internal clock that eliminates the

need of synchronization between the external clock and

the CS and RD signals found in other ADCs. The internal

clock is factory trimmed to achieve a typical conversion

time of 1.4

µs. No external adjustments are required, and

with the typical acquisition time of 160ns, throughput

performance of 600ksps is assured.

Power Shutdown

The LTC1279 provides a power shutdown feature that

saves power when the ADC is in inactive periods. To power

down the ADC, pin 18 (SHDN) needs to be driven low.

When in power shutdown mode, the LTC1279 will not start

a conversion even though the CONVST goes low. All the

power is off except the Internal Reference which is still

active and provides 2.42V output voltage to the other

circuitry. In this mode the ADC draws 8.5mW instead of

60mW (for minimum power, the logic inputs must be

within 600mV of the supply rails). The wake-up time from

the power shutdown to active state is 350ns.

Figure 10. Power Supply Grounding Practice

1279 F10

AGND

DGND

LTC1279

DIGITAL

SYSTEM

0.1

µF

+

–

ANALOG GROUND PLANE

GROUND CONNECTION

TO DIGITAL CIRCUITRY

ANALOG

INPUT

CIRCUITRY

3

2

24

17

12

1

0.1

µF

10

µF

10

µF