LTC1290BCSW datasheet(21/28 Pages) LINER

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LTC1290

APPLICATI

I FOR ATIO

Differential Inputs

With differential inputs or when the COM pin is not tied to

ground, the A/D no longer converts just a single voltage but

rather the difference between two voltages. In these cases,

the voltage on the selected “+” input is still sampled and held

and therefore may be rapidly time varying just as in single-

ended mode. However, the voltage on the selected “–” input

must remain constant and be free of noise and ripple

throughout the conversion time. Otherwise, the differencing

operation may not be performed accurately. The conversion

time is 52 ACLK cycles. Therefore, a change in the “–” input

voltage during this interval can cause conversion errors.

For a sinusoidal voltage on the “–” input this error would be:

VERROR (MAX) = (VPEAK)(2π)[ f(“–”)](52/fACLK)

Where f(“–”) is the frequency of the “–” input voltage,

VPEAK is its peak amplitude and fACLK is the frequency of

the ACLK. In most cases VERROR will not be significant. For

a 60Hz signal on the “–” input to generate a 0.25LSB error

(300

µV) with the converter running at ACLK = 4MHz, its

peak value would have to be 61mV.

5. Reference Inputs

The voltage between the reference inputs of the LTC1290

defines the voltage span of the A/D converter. The refer-

ence inputs will have transient capacitive switching cur-

rents due to the switched capacitor conversion technique

(see Figure 14). During each bit test of the conversion

(every 4 ACLK cycles), a capacitive current spike will be

generated on the reference pins by the A/D. These current

spikes settle quickly and do not cause a problem. How-

ever, if slow settling circuitry is used to drive the reference

inputs, care must be taken to insure that transients caused

by these current spikes settle completely during each bit

test of the conversion.

Figure 14. Reference Input Equivalent Circuit

RON

8pF TO 40pF

LTC1290

REF+

ROUT

VREF

EVERY 4 ACLK CYCLES

REF–

LTC 1290 F14

When driving the reference inputs, two things should be

kept in mind:

1. Transients on the reference inputs caused by the

capacitive switching currents must settle completely

during each bit test (each 4 ACLK cycles). Figures 15

and 16 show examples of both adequate and poor

settling. Using a slower ACLK will allow more time for

the reference to settle. However, even at the maximum

ACLK rate of 4MHz most references and op amps can

be made to settle within the 1

µs bit time. For example

the LT1027 will settle adequately or with a 10

µFbypass

capacitor at REF + the LT1021 can also be used.

2. It is recommended that REF– input be tied directly to

the analog ground plane. If REF– is biased at a voltage

other than ground, the voltage must not change during

a conversion cycle. This voltage must also be free of

noise and ripple with respect to analog ground.

Figure 16. Poor Reference Settling Can Cause A/D Errors

HORIZONTAL: 1

µs/DIV

Figure 15. Adequate Reference Settling

HORIZONTAL: 1

µs/DIV

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