5

LTC1350

PI FU CTIO S

35

µA in the SHUTDOWN mode. This pin should be de-

coupled with a 0.1

µF ceramic capacitor.

GND: Ground Pin.

ON/OFF: TTL/CMOS Compatible Shutdown Pin. A logic

low puts the device in the SHUTDOWN mode with receiv-

ers 4 and 5 kept alive and the supply current equal to 35

µA.

All driver and other receiver outputs are in high impedance

state. This pin cannot float.

requires an external capacitor (C = 0.1

µF) for charge

common capacitors. For a large number of devices, in-

creasing the size of the shared common storage capaci-

tors is recommended to reduce ripple.

pin requires an external capacitor (C = 0.1

µF) for charge

storage.

SWITCHI G TI E WAVEFOR S

1.4V

0V

0V

0V

DR

INPUT

DR

OUTPUT

1.4V

LTC1350 • F01

0.8V

0V

2.4V

RX

INPUT

RX

OUTPUT

1.3V

1.7V

LTC1350 • F02

0V

Figure 2. Receiver Propagation Delay Timing

Figure 1. Driver Propagation Delay Timing

pins require two external capacitors (C = 0.1

µF): one from

charge pump efficiency, the capacitor’s effective series

resistance should be less than 20

Ω.

DR IN: EIA/TIA-562 Driver Input Pins. Inputs are TTL/

CMOS compatible. Inputs should not be allowed to float.

DR OUT: Driver Outputs at EIA/TIA-562 Voltage Levels.

Outputs are in a high impedance state when in the SHUT-

against ESD to

±10kV for human body model discharges.

RX IN: Receiver Inputs. These pins can be forced to

±25V

without damage. The receiver inputs are protected against

ESD to

±10kV for human body model discharges. Each

receiver provides 0.4V of hysteresis for noise immunity.

RX OUT: Receiver Outputs with TTL/CMOS Voltage Lev-

els. Receiver 1, 2 and 3 outputs are in a high impedance

state when in SHUTDOWN mode to allow data line sharing.

Receivers 4 and 5 are kept alive in SHUTDOWN.