8

LTC1429

the clock pulse finishes. When this happens, the compara-

tor will allow a few complete pulses through, then over-

correct and disable the charge pump until the output

drops below the set point. Under these conditions, the

output will remain in regulation, but the output ripple will

increase as the comparator “hunts” for the correct value.

To help prevent this from happening, an external capacitor

can be connected from ADJ (or COMP for fixed output

parts) to ground to compensate for external parasitics and

increase the regulation loop bandwidth (Figure 5). This

sounds counter-intuitive until we remember that the inter-

nal reference is generated with respect to OUT, not ground.

The feedback loop actually sees ground as its “output”;

thus the compensation capacitor should be connected

across the “top” of the resistor divider from ADJ (or

COMP) to ground. By the same token, avoid adding

slow down the feedback loop and increase output ripple.

A 1000pF capacitor from ADJ or COMP to ground will

compensate the loop properly under most conditions.

current. The clock signal should have a duty cycle between

40% and 60% for proper regulation loop performance.

The LTC 1429 can be shut down by stopping the clock. An

internal circuit monitors the time between clock edges at

the SYNC/SD pin. If a 10

µs period elapses without a rising

or falling edge, LTC1429 assumes the clock has stopped

and goes into shutdown mode and the quiescent current

drops to below 1

µA. The next clock edge at the SYNC/SD

pin will reawaken the LTC1429. At clock frequencies

below 50kHz (50% duty cycle) the LTC1429 may enter

shutdown mode briefly during each clock cycle causing

erratic operation. Minimum operating frequency should

prevent this from happening.

Radiation from the clock signal at the SYNC/SD pin can

interfere with the feedback node at the ADJ/COMP pin

causing errors in the output voltage. The clock line should

be routed away from the circuitry at the ADJ/COMP pin

and should be shielded with a ground plane or with coaxial

cable. A compensation capacitor from the ADJ/COMP pin

to ground can also help to reduce this effect: 0.001

µF is

adequate for most applications.

OUTPUT FILTERING

If extremely low output ripple (< 10mV) is required, addi-

tional output filtering is required. Because the LTC1429

uses a high, external control switching frequency, fairly

low value RC or LC networks can be used at the output to

10

Ω series output resistor and a 3.3µF capacitor will cut

output ripple to below 3mV (see Figure 6). Further reduc-

COMP 1

1.24V

R2

ADJ/COMP

RESISTORS ARE INTERNAL

FOR FIXED OUTPUT PARTS

LTC1429 • F05

R1

1000pF

TO CHARGE

PUMP

REF

+

–

Figure 5. Regulator Loop Compensation

EXTERNAL CLOCK

The LTC1429 requires an external clock to operate. This

clock signal should be TTL or CMOS compatible and

should be applied to the SYNC/SD pin. The external clock

allows the user to control the frequency at which the

LTC1429 operates, preventing it from interfering with

other frequency-sensitive circuitry. The LTC1429 can be

synchronized to any frequency between 60kHz (100kHz

reduce output ripple at the cost of additional quiescent

LTC1429CS8-4

5V

4

1

6

8

5

2

3

OUT

SYNC/SD

0.1

µF

1000pF

3.3

µF

10

Ω

COMP

LTC1429 • F06

GND

3.3

µF

0.1

µF

Figure 6. Output Filter Cuts Ripple Below 3mV