13

LTC1430

S

APPLICATI

I FOR ATIO

Oscillator Frequency

The LTC1430 includes an onboard current controlled

oscillator which will typically free-run at 200kHz. An

internal 20

µA current is summed with any current in or out

of the FREQSET pin (pin 11), setting the oscillator fre-

quency to approximately 10kHz/

µA. FREQSET is internally

servoed to the LTC1430 reference voltage (1.26V). With

FREQSET floating, the oscillator is biased from the internal

20

µA source and runs at 200kHz. Connecting a 50k

resistor from FREQSET to ground will sink an additional

25

µA from FREQSET, causing the internal oscillator to run

at approximately 450kHz. Sourcing an external 10

µA

current into FREQSET will cut the internal frequency to

100kHz. An internal clamp prevents the oscillator from

will cause it to run at this minimum speed.

Shutdown

The LTC1430 includes a low power shutdown mode,

controlled by the logic at the SHDN pin. A high at SHDN

allows the part to operate normally. A low level at SHDN

stops all internal switching, pulls COMP and SS to ground

internally and turns M1 and M2 off. In shutdown, the

LTC1430 itself will drop below 1

µA quiescent current

typically, although off-state leakage in the external

what higher, especially at elevated temperatures. When

SHDN rises again, the LTC1430 will rerun a soft-start cycle

and resume normal operation. Holding the LTC1430 in

sequencing constraints.

LAYOUT CONSIDERATIONS

Grounding

Proper grounding is critical for the LTC1430 to obtain

specified output regulation. Extremely high peak currents

(as high as several amps) can flow between the bypass

currents can generate significant voltage differences be-

tween two points that are nominally both “ground.” As a

general rule, GND and PGND should be totally separated

on the layout, and should be brought together at only one

point, right at the LTC1430 GND and PGND pins. This

helps minimize internal ground disturbances in the

LTC1430 by keeping PGND and GND at the same potential,

while preventing excessive current flow from disrupting

the operation of the circuits connected to GND. The PGND

node should be as compact and low impedance as pos-

sible, with the negative terminals of the input and output

capacitors, the source of M2, the LTC1430 PGND node,

the output return and the input supply return all clustered

at one point. Figure 11 is a modified schematic showing

the common connections in a proper layout. Note that at

10A current levels or above, current density in the PC

board itself can become a concern; traces carrying high

currents should be as wide as possible.

Output Voltage Sensing

The LTC1430 provides three pins for sensing the output

connect to an internal resistor divider which is connected

to FB. To set the output of the LTC1430 to 3.3V, connect

is just the bottom of the internal divider string. Connecting

string should be connected to FB (Figure 12). As before,

connect the top resistor (R1) to the output as close to the

load as practical and connect the bottom resistor (R2) to

the common GND/PGND point. In both cases, connecting

to the load can significantly improve load regulation by

compensating for any drops in PC traces or hookup wires

between the LTC1430 and the load.

Power Component Hook-Up/Heat Sinking

As current levels rise much above 1A, the power compo-

nents supporting the LTC1430 start to become physically

large (relative to the LTC1430, at least) and can require

special mounting considerations. Input and output ca-

pacitors need to carry high peak currents and must have

low ESR; this mandates that the leads be clipped as short

as possible and PC traces be kept wide and short. The