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LTC1434IGN 数据表(PDF) 13 Page - Linear Technology |
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LTC1434IGN 数据表(HTML) 13 Page - Linear Technology |
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13 / 20 page ![]() 13 LTC1433/LTC1434 APPLICATIONS INFORMATION further reducing the current to 15 µA. The low side of the resistive divider should connect to SGND. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1433/LTC1434. These items are also illustrated graphi- cally in the layout diagram of Figure 13. Check the follow- ing in your layout: 1. Are the signal and power grounds segregated? The LTC1433/LTC1434 signal ground pin must return to the (–) plate of COUT. The power ground returns to the anode of the Schottky diode and the (–) plate of CIN, which should have as short lead lengths as possible. 2. Does the LTC1433/LTC1434 VOSENSE pin connect to the (+) plate of COUT? In adjustable applications, the resis- tive divider R1/R2 must be connected between the (+) plate of COUT and signal ground. 3. Does the (+) plate of CIN connect to the power VIN as close as possible? This capacitor provides the AC current to the internal P-channel MOSFETs and their drivers. 4. Is the Schottky diode closely connected between the power ground and switch pin? 5. Keep the switching nodes, SSW and BSW away from sensitive small-signal nodes VOSENSE, PLLIN, PLL LPF, COSC, ITH and LBI. Design Example As a design example, assume VIN = 6V, VOUT = 5V, IMAX = 400mA and fOSC = 200kHz. With these requirements we can start choosing all of the important components. With no frequency synchronization required, the LTC1433 can be used for this circuit. From Figure 2, the VPLL LPF = 0V curve is used to determine the value of the oscillator capacitor. From the graph a value of 50pF will provide the desired frequency. Next the inductor value is selected. From the Maximum Output Current vs Input Supply graph in the Typical Performance Characteristics section, a value of L = 22 µH would be able to meet the requirement for the output load current. For the catch diode, a MBRS130LT3 is selected. Figure 13. LTC1434 Layout Diagram (See Board Layout Check List) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC SSW NC BSW SGND NC RUN/SS NC LBO LBI PWRVIN SVIN PLLIN PLL LPF COSC POR ITH VOSENSE VPROG LTC1434 PGND CIN CSS 0.1 µF OUTPUT DIVIDER REQUIRED WITH ADJUSTABLE VERSION ONLY. CONNECT VOSENSE TO VOUT FOR FIXED OUTPUT VOLTAGE VOUT COUT D1 L1 1433/34 F13 COSC + BOLD LINES INDICATE HIGH CURRENT PATHS |
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