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LTC1446CS8 数据表(PDF) 3 Page - Linear Technology |
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LTC1446CS8 数据表(HTML) 3 Page - Linear Technology |
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3 / 12 page ![]() 3 LTC1446/LTC1446L VCC = 4.5V to 5.5V (LTC1446), 2.7V to 5.5V (LTC1446L), VOUT A and VOUT B unloaded, TA = TMIN to TMAX, unless otherwise noted. ELECTRICAL CHARACTERISTICS VCC = 5V (LTC1446), VCC = 3V (LTC1446L), TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Op Amp DC Performance Short-Circuit Current Low VOUT Shorted to GND q 55 120 mA Short-Circuit Current High VOUT Shorted to VCC q 70 120 mA Output Impedance to GND Input Code = 0 q 40 120 Ω AC Performance Voltage Output Slew Rate (Note 2) q 0.5 1 V/ µs Voltage Output Settling Time (Notes 2, 3) to ±0.5LSB 14 µs The q denotes specifications which apply over the full operating temperature range. Note 1: Nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to code 4095 (full scale). Note 2: Load is 5k Ω in parallel with 100pF. Note 3: DAC switched between all 1s and the code corresponding to VOS for the part. Note 4: Digital inputs at 0V or VCC. LTC1446 LTC1446L SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Digital I/O VIH Digital Input High Voltage q 2.4 2 V VIL Digital Input Low Voltage q 0.8 0.6 V VOH Digital Output High Voltage IOUT = – 1mA q VCC – 1.0 VCC – 0.7 V VOL Digital Output Low Voltage IOUT = 1mA q 0.4 0.4 V ILEAK Digital Input Leakage VIN = GND to VCC q ±10 ±10 µA CIN Digital Input Capacitance Guaranteed by Design q 10 10 pF Switching t1 DIN Valid to CLK Setup q 40 60 ns t2 DIN Valid to CLK Hold q 00 ns t3 CLK High Time q 40 60 ns t4 CLK Low Time q 40 60 ns t5 CS/LD Pulse Width q 50 80 ns t6 LSB CLK to CS/LD q 40 60 ns t7 CS/LD Low to CLK q 20 30 ns t8 DOUT Output Delay CLOAD = 15pF q 150 220 ns t9 CLK Low to CS/LD Low q 20 30 ns |
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