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LTC1472CS 数据表(PDF) 3 Page - Linear Technology

部件名 LTC1472CS
功能描述  Protected PCMCIA VCC and VPP Switching Matrix
PDF  16 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC1472CS 数据表(HTML) 3 Page - Linear Technology

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LTC1472
VDD = 5V, VCC(IN) = 5V, VPPIN = 12V, VCCEN0 = VCCEN1 = 0V, TA= 25°C, (Note 1), unless otherwise noted.
The q denotes the specifications which apply over the full operating
temperature range.
Note 1: VENH = 5V, VENL = 0V. See VCC and VPP Switch Truth Tables for
programming enable inputs for desired output states.
Note 2: Power for the VCC input logic and charge pump circuitry is derived
from the 5VIN power supply which must be continuously powered. 12V
and 3.3V power is not required to control the NMOS VCC switches. (See
Applications Information.)
Note 3: The two 3VIN supply input pins (14 and 15) must be connected
together and the two VCC(OUT) output pins (1 and 16) must be connected
together. The 3VIN supply pins do not need to be continuously powered
and may drop to 0V when not required.
Note 4: The VCC and VPP output are protected with foldback current limit
which reduces the short-circuit (0V) currents below peak permissible
current levels at higher output voltages.
Note 5: To 90% of final value.
Note 6: 12V power is only required when VPPOUT is programmed to 12V.
The external 12V regulator can be shutdown at all other times. Built-in
charge pumps power the internal NMOS switches from the 5V VDD supply
when 12V is not present.
Note 7: Power for the VPP input logic and charge pump circuitry is derived
from the VDD power supply which must be continuously powered.
Note 8: To 90% of the final value, COUT = 0.1µF, ROUT = 2.9k.
Note 9: To 10% of the final value, COUT = 0.1µF, ROUT = 2.9k.
Note 10: To 50% of the initial value, COUT = 0.1µF, ROUT = 2.9k.
ELECTRICAL CHARACTERISTICS (VPP Switch Section)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC(IN)
VCC Input Voltage Range
q
3
5.5
V
VPPIN
VPP Input Voltage Range
(Note 6)
q
0
12.6
V
VDD
Logic Supply Voltage Range
(Note 7)
q
4.5
5.5
V
ICCIN
VCC(IN) Supply Current, No Load
Program to VPPIN or VCC(IN) VPPIN = 12V
q
35
60
µA
Program to 0V or Hi-Z
q
0.01
10
µA
IPPIN
VPPIN Supply Current, No Load
Program to VPPIN or VCC(IN)
q
40
80
µA
Program to 0V or Hi-Z
q
0.01
10
µA
IDD
VDD Supply Current, No Load
Program to VPPIN
q
70
120
µA
Program to VCC(IN), VPPIN = 0V
q
85
150
µA
Program to VCC(IN), VPPIN = 12V
q
40
80
µA
Program to 0V or Hi-Z
q
0.01
10
µA
IVPPOUT
Hi-Z Output Leakage Current
Program to Hi-Z, 0V < VPPOUT < 12V
q
0.01
10
µA
RON
On Resistance VPPOUT to VPPIN
VPPIN = 12V, ILOAD = 120mA
0.50
1
On Resistance VPPOUT to VCC(IN)
VCC(IN) = 5V, ILOAD = 5mA
1.70
5
On Resistance VPPOUT to GND
VDD = 5V, ISINK = 1mA
100
250
VPPENH
VPP Enable Input High Voltage
VDD = 5V
q
2V
VPPENL
VPP Enable Input Low Voltage
VDD = 5V
q
0.8
V
IVPPEN
VPP Enable Input Current
0V < VPP EN < VDD
q
±1
µA
VSDH
SHDN Output High Voltage
Program to 0V, VCC(IN) or Hi-Z, ILOAD = 400µA
q
3.5
V
VSDL
SHDN Output Low Voltage
Program to VPPIN, ISINK = 400µA
q
0.4
V
ILIMVCC
VPPOUT Current Limit, VCC(IN)
Program to VCC(IN), VPPOUT = 0V (Note 4)
60
mA
ILIMVPP
VPPOUT Current Limit, VPPIN
Program to VPPIN, VPPOUT = 0V (Note 4)
100
mA
tVPP1
Delay and Rise Time
From 0V to VCC(IN),VPPIN = 0V (Note 8)
5
15
50
µs
tVPP2
Delay and Rise Time
From 0V to VPPIN (Note 8)
25
85
250
µs
tVPP3
Delay and Rise Time
From VCC(IN) to VPPIN (Note 8)
30
100
300
µs
tVPP4
Delay and Fall Time
From VPPIN to VCC(IN) (Note 9)
5
15
50
µs
tVPP5
Delay and Fall Time
From VPPIN to 0V (Note 10)
10
35
100
µs
tVPP6
Delay and Fall Time
From VCC(IN) to 0V, VPPIN = 0V (Note 10)
10
30
100
µs
tVPP7
Output Turn-On Delay
From Hi-Z to VCC(IN) (Note 8)
5
15
50
µs
tVPP8
Output Turn-On Delay
From Hi-Z to VPPIN (Note 8)
25
85
250
µs



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