11

LTC1504

frequency. Attempting to synchronize to a frequency

lower than the 250kHz maximum internal frequency may

result in inconsistent pulse widths and is not recom-

mended.

Because the sawtooth waveform rises at a fixed rate

internally, terminating it early by synchronizing to a fast

external clock will reduce the amplitude of the sawtooth

wave that the PWM comparator sees, effectively raising

the gain from COMP to SW. 500kHz is the maximum

recommended synchronization frequency; higher frequen-

cies will reduce the sawtooth amplitude to the point that

the LTC1504 may run erratically.

THERMAL CONSIDERATIONS

Each of the LTC1504 internal power switches has approxi-

mately 1.5

Ω of resistance at room temperature and will

happily carry more than the rated maximum current if the

current limit is set very high or is not connected. Since the

inductor current is always flowing through one or the

other of the internal switches, a typical application supply-

ing 500mA of load current will cause a continuous dissi-

pation of approximately 375mW. The SO-8 package has a

thermal resistance of approximately 90

°C/W, meaning

that the die will begin to rise toward 34

°C above ambient

increases as the die temperature rises, increasing the

power dissipation as the feedback loop continues to keep

the output current at 500mA. At high ambient tempera-

tures, this cycle may continue until the chip melts, since

the LTC1504 does not include any form of thermal shut-

down. Applications can safely draw peak currents above

the 500mA level, but the average power dissipation should

be carefully calculated so that the maximum 115

°C die

temperature is not exceeded.

The LTC1504 dissipates the majority of its heat through its

pins, especially GND (Pin 4). Thermal resistance to ambi-

ent can be optimized by connecting GND to a large copper

region on the PCB, which will serve as a heat sink.

Applications which will operate the LTC1504 near maxi-

mum power levels or which must withstand short circuits

of extended duration should maximize the copper area at

all pins and ensure that there is some airflow over the part

to carry away excess heat. For layout assistance in situa-

tions where power dissipation may be a concern, contact

the LTC Applications Department.

The current limit circuit can be used to limit the power

under mild overloads to a safe level, but severe overloads

where the output is shorted to ground may still cause the die

temperature to rise dangerously. For more information on

current limit behavior, see the Current Limit section.

LAYOUT CONSIDERATIONS

Like all precision switching regulators, the LTC1504

requires special care in layout to ensure optimum perfor-

mance. The large peak currents coupled with significant

DC current flow will conspire to keep the output from

regulating properly if the layout is not carefully planned. A

poorly laid out op amp or data converter circuit will fail to

give the desired performance, but will usually still act like

an op amp or data converter. A poorly laid out LTC1504

circuit may look nothing at all like a regulator.

Wire-wrap

or plug-in prototyping boards are not useful for bread-

boarding LTC1504 circuits!

Perhaps most critical to proper LTC1504 performance is

the layout of the ground node and the location of the input

and output capacitors. The negative terminals of both the

input and output bypass capacitors should come together

at the same point, as close as possible to the LTC1504

ground pin. The compensation network and soft start

capacitor can be connected together on their own trace,

which should come directly back to this same common

ground point. The input supply ground and the load return

should also connect to this common point. Each ground

line should come to a star connection with Pin 4 at the

center of the star. This node should be a fairly large copper

region to act as a heat sink if required.

Second in importance is the proximity of the low ESR (usually

ceramic) input bypass capacitor. It should be located as close

Ideally, the capacitor should be located right next to the

package, straddling the SW pin. High peak current applica-

1

µF or larger ceramic capacitor in this position.

One node that isn’t quite so critical is SW. Extra lead length

or narrow traces at this pin will only add parasitic induc-