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LTC1553LCSW 数据表(PDF) 13 Page - Linear Technology |
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LTC1553LCSW 数据表(HTML) 13 Page - Linear Technology |
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13 / 20 page ![]() 13 LTC1553L APPLICATIONS INFORMATION R P DC Q I VP VI R P DC Q I VP VV I DS ON Q MAX Q MAX IN MAX Q OUT MAX DS ON Q MAX Q MAX IN MAX Q IN OUT MAX () () () () () () = () []() = () ()( ) = () []() = () − ()( ) 1 1 2 1 2 2 2 2 2 2 1 2 PMAX should be calculated based primarily on required efficiency or allowable thermal dissipation. A typical high efficiency circuit designed for Pentium II with a 5V input and a 2.8V, 11.2A output might allow no more than 4% efficiency loss at full load for each MOSFET. Assuming roughly 90% efficiency at this current level, this gives a PMAX value of: [(2.8)(11.2A/0.9)(0.04)] = 1.39W per FET and a required RDS(ON) of: R VW VA R VW VV A DS ON Q DS ON Q () () = ()( ) ()( ) = = ()( ) − ()( ) = 1 2 2 2 51 39 2 8 11 2 0 019 51 39 52 8 11 2 0 025 . .. . . .. . Ω Ω Note also that while the required RDS(ON) values suggest large MOSFETs, the dissipation numbers are only 1.39W per device or less––large TO-220 packages and heat sinks are not necessarily required in high efficiency applica- tions. Siliconix Si4410DY or International Rectifier IRF7413 (both in SO-8) or Siliconix SUD50N03 or Motorola MTD20N03HDL (both in D PAK) are small footprint sur- face mount devices with RDS(ON) values below 0.03Ω at 5V of gate drive that work well in LTC1553L circuits. With higher output voltages, the RDS(ON) of Q1 may need to be significantly lower than that for Q2. These conditions can often be met by paralleling two MOSFETs for Q1 and using a single device for Q2. Note that using a higher PMAX value in the RDS(ON) calculations will generally decrease MOSFET cost and circuit efficiency while increasing MOSFET heat sink requirements. Q1 G1 Q2 0.1 µF LO VOUT 1553L F07 COUT CIN VIN PVCC 1N5243B 13V 1N5817 OPTIONAL FOR VIN > 5V G2 LTC1553L 20 1 2 + + Figure 7. Doubling Charge Pump If the OUTEN pin is low, G1 and G2 are both held low to prevent output voltage undershoot. As VCC and PVCC power up from a 0V condition, an internal undervoltage lockup circuit prevents G1 and G2 from going high until VCC reaches about 3.5V. If VCC powers up while PVCC is at ground potential, the SS is forced to ground potential internally. SS clamps the COMP pin low and prevents the drivers from turning on. On power-up or recovery from thermal shutdown, the drivers are designed such that G2 is held low until G1 first goes high. Power MOSFETs Two N-channel power MOSFETs are required for most LTC1553L circuits. Logic level MOSFETs should be used and they should be selected based on on-resistance con- siderations. RDS(ON) should be chosen based on input and output voltage, allowable power dissipation and maxi- mum required output current. In a typical LTC1553L buck converter circuit the average inductor current is equal to the output load current. This current is always flowing through either Q1 or Q2 with the power dissipation split up according to the duty cycle: DC Q V V DC Q V V VV V OUT IN OUT IN IN OUT IN 1 21 ()= ()=− = − () The RDS(ON) required for a given conduction loss can now be calculated by rearranging the relation P = I2R. |
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