5

LTC1590

enabled so the data can be clocked in. When CS/LD is

pulled high, data is loaded from the shift register into the

DAC register, updating the DAC output.

on the rising edge of the CLK.

latched into the shift register on the rising edge of the serial

clock. Data is loaded as one 24-bit word. The first 12 bits

are for DAC A, MSB-first and the second 12 bits are for

DAC B, MSB-first.

CLK (Pin 14): The Serial Interface Clock Input.

CLR (Pin 15): The Clear Pin for the DAC. Clears both DACs

to zero scale when pulled low. This pin should be tied to

≤ 5.5V. Requires a bypass capacitor to ground.

Typically

±10V, accepts up to ±25V.

Normally tied to the output of current to voltage converter

op amp. Typically swings to

±10V. Swings from 0V to

OUT1 B, OUT1 A (Pins 3, 6): True Current Output for DAC

A/B. Normally tied to inverting input of current to voltage

converter op amp.

OUT2 B, OUT2 A (Pins 4, 5): Complement Current Output

for DAC A/B. Normally tied to ground.

AGND (Pin 7): Analog Ground Pin. Tie to ground.

DGND (Pin 10): Digital Ground Pin. Tie to ground.

CS/LD (Pin 11): The Serial Interface Enable and Load

Control Input. When CS/LD is low the CLK signal is

INPUT VOLTAGE (V)

0

1.0

0.5

0

4

1590 G01

1

2

3

5

Supply Current vs

Logic Input Voltage

TIME (500ns/DIV)

1590 G11

LT1363 OP AMP

SUPPLY VOLTAGE (V)

0

4

3

2

1

0

510

1590 G04

15

Logic Threshold vs

Supply Voltage

Midscale Glitch Impulse