LTC1606AI datasheet(6/12 Pages) LINER

6 / 12 page

LTC1606

PIN FUNCTIONS

CS (Pin 25): Chip Select. Internally OR’d with R/C. With

R/C low, a falling edge on CS will initiate a conversion.

With R/C high, a falling edge on CS will enable the output

data.

BUSY (Pin 26): Output Shows Converter Status. It is low

when a conversion is in progress. Data valid on the rising

edge of BUSY. CS or R/C must be high when BUSY rises

TEST CIRCUITS

Load Circuit for Access Timing

30pF

DBN

1606 TC01

A. Hi-Z TO VOH AND VOL TO VOH

B. Hi-Z TO VOL AND VOH TO VOL

Load Circuit for Output Float Delay

30pF

DBN

1606 TC02

A. VOH TO Hi-Z

B. VOL TO Hi-Z

FUNCTIONAL BLOCK DIAGRA

16-BIT CAPACITIVE DAC

COMP

REF BUF

1.64x

2.5V REF

CAP

(4.096V)

CSAMPLE

•

D15

BUSY

CONTROL LOGIC

R/C

BYTE

INTERNAL

CLOCK

ZEROING SWITCHES

VDIG

VANA

VIN

REF

AGND1

AGND2

DGND

1606 BD

–

SUCCESSIVE APPROXIMATION

OUTPUT LATCHES

7.35k

2.5k

or another conversion will start without time for signal

acquisition.

VANA (Pin 27): 5V Analog Supply. Bypass to ground with

a 0.1

µF ceramic and a 10µF tantalum capacitor.

VDIG (Pin 28): 5V Digital Supply. Connect directly to Pin

27.

LTC1606AI 数据表(PDF) 6 Page - Linear Technology

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